ESD Protection Circuit Trigger Efficiency and Latch-up Inhibition
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Solution Overview
Problem
Deep submicron integrated circuits (ICs) are vulnerable to electrostatic discharge (ESD) due to their increased sensitivity and the bulky discharge transistors used in existing ESD protection circuits, which lead to inefficiencies and a higher risk of latch-up, affecting reliability.
Innovation Solution
An ESD protection circuit incorporating an RC trigger circuit, a transmission gate, and a silicon-controlled rectifier with low resistance values, utilizing a series connection of inverters and transistors to improve trigger efficiency and prevent latch-up, including a pull-up and pull-down transistor configuration to inhibit latch-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bulky discharge transistor is used in existing ESD protection circuits, then the ESD protection capability is improved, but the circuit footprint increases and integration density decreases
Solution Approach 1:
The discharge transistor is segmented into multiple smaller transistors arranged in a specific configuration. Instead of using one large discharge transistor, the patent divides it into several smaller units that work together to provide the same ESD protection capability while occupying less total area and improving integration density.
2Reliability
If a bulky discharge transistor is used in existing ESD protection circuits, then the ESD protection capability is improved, but the leakage current increases affecting circuit operation
Solution Approach 1:
The discharge transistor is segmented into multiple smaller transistors arranged in a specific configuration. Instead of using one large discharge transistor, the patent divides it into several smaller units that work together to provide the same ESD protection capability while occupying less total area and improving integration density.
3Reliability
If existing ESD protection circuits are used, then ESD protection is provided, but the trigger efficiency is low and latch-up risk is high
Solution Approach 1:
The patent introduces an intermediary circuit between the ESD event detection point and the discharge transistor control. This intermediary circuit processes the trigger signal more efficiently, improving the response time and trigger efficiency while reducing the risk of latch-up conditions.
Solution Approach 2:
The patent modifies key parameters of the ESD protection circuit, including the threshold voltages, transistor dimensions, and resistance values, to optimize the trigger efficiency and prevent latch-up while maintaining adequate ESD protection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances ESD protection trigger efficiency and reduces the likelihood of latch-up, ensuring reliable operation by effectively discharging ESD currents while maintaining low resistance values and preventing latch-up.
Implementation Method 1
an RC trigger circuit formed of a resistor RI and a capacitor C1
Implementation Method 2
an RC trigger circuit formed of a resistor RI and a capacitor C1
Implementation Method 3
The transmission gate includes an nMOS transistor and a pMOS transistor connected in parallel
Implementation Method 4
a discharge transistor 20. The discharge transistor 20 is realized as an nMOS transistor... a very large current flowing through the IC chip in a very short period of time
Data Source
AI summary
An ESD protection circuit is disclosed, in which an RC trigger circuit and a transmission gate are used for determination of ESD protection triggering, and a silicon-controlled rectifier for ESD current conductance. The RC trigger circuit and the transmission gate allow improved trigger efficiency. In addition, the silicon-controlled rectifier incorporates first and second resistors, which can be implemented to have very low resistance values and are therefore able to effectively prevent the occurrence of latch-up during normal operation, as well as pull-up and pull-down transistors which can make an additional contribution to latch-up inhibition when turned on.