ESD Protection Device Uniform Activation

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Solution Overview

Problem

Existing ESD protection devices, such as GGNMOS, face challenges in uniformly dispersing ESD current due to varying substrate resistance among elementary transistors, leading to incomplete discharge and limited scalability of ESD tolerance with device width.

Innovation Solution

The ESD protection device incorporates a substrate with specific doping regions and shallow trench isolators to ensure uniform activation of elementary MOS transistors, preventing secondary snapback and maintaining holding voltage above operation levels, thereby allowing each transistor to uniformly disperse ESD current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a multi-finger structure is adopted to conserve IC layout region, then the device width is increased to tolerate higher ESD current, but the elementary transistors cannot turn on uniformly due to different substrate resistance, causing latch up and limiting ESD current dispersion

Engineering Contradiction:
ImproveESD current toleranceVSAvoidUniform activation of elementary transistors
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent introduces a well structure (third doping region) beneath the drain structure with doping concentration greater than the drift region, creating localized electrical property modification. This local quality change equalizes the substrate resistance experienced by each elementary transistor in the multi-finger structure, enabling uniform turn-on behavior while maintaining high ESD current tolerance.

Inventive Principle:
Principle #3Local quality

2Productivity

If the gate oxide thickness is scaled down to improve device performance, then the transistor size is reduced, but the gate oxide becomes more vulnerable to breakdown from ESD stress

Engineering Contradiction:
ImproveDevice performanceVSAvoidGate oxide breakdown susceptibility
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent designs the well structure with specific doping concentration and depth beforehand to create a protective electrical environment. This prior cushioning mechanism ensures that even when gate oxide is scaled down for better performance, the underlying well structure provides electrical stabilization that prevents premature breakdown during ESD events.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly increases ESD current tolerance and allows the ESD protection capacity to scale linearly with device width, preventing 'latch up' and ensuring effective ESD current dispersion in multi-finger structures.

Implementation Method 1

The first doping region has a first doping concentration, the second doping region has a second doping concentration substantially greater than the first doping concentration, and the third doping region has a third doping concentration substantially greater than the first doping concentration

Methodology Applied
Scientific EffectDoping: Dopants

Data Source

PatentUS8492834B2Electrostatic discharge protection device and applications thereof
Publication Date: 2013.07.23 UNITED MICROELECTRONICS CORP
  • US8492834B2 patent drawing
  • US8492834B2 patent drawing
  • US8492834B2 patent drawing

AI summary

An electrostatic discharge protection device comprises a substrate with a first conductivity, a gate, a drain structure and a source structure. The gate is disposed on a surface of the substrate. The drain structure with a second conductivity type comprises a first doping region with a first doping concentration disposed adjacent to the gate and extending into the substrate from the surface of the substrate, a second doping region extending into and stooped at the first doping region from the surface of the substrate and having a second doping concentration substantially greater than the first doping concentration, and a third doping region disposed in the substrate beneath the second doping region and having a third doping concentration substantially greater than the first doping concentration. The source structure with the second conductivity is disposed in the substrate and adjacent to the gate electrode.