ESD Protection Apparatus with Localized Doping for Uniform MOS Triggering

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Solution Overview

Problem

Multi-finger-shaped MOS transistors in semiconductor integrated circuits suffer from non-uniform triggering due to varying distances from the I/O pad, leading to concentrated ESD current discharge and potential damage, as existing designs struggle to improve triggering uniformity without increasing layout size.

Innovation Solution

An ESD protection apparatus is designed with a semiconductor substrate featuring a doping well, a first gate structure, and doping regions with specific conductivity levels and concentrations, forming a P/N junction interface to facilitate uniform triggering of MOS transistors, allowing ESD current to be directed into the ground and reducing breakthrough voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If multi-finger-shaped MOS transistors are used to improve ESD tolerance and save layout size, then the layout size is reduced and ESD tolerance is improved, but the triggering uniformity deteriorates due to varying distances from the I/O pad

Engineering Contradiction:
Improvelayout sizeVSAvoidtriggering uniformity
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent introduces a doping region with a third conductivity type that is different from both the doping well and the MOS transistor conductivity types. This creates localized P/N junction interfaces at specific positions between the MOS transistor and I/O pad, providing non-uniform electric field distribution that compensates for the distance variation effect, thereby improving triggering uniformity while maintaining the multi-finger structure's compact layout advantage

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If multi-finger-shaped MOS transistors are used to improve ESD tolerance and save layout size, then the layout size is reduced, but the ESD current concentration worsens leading to potential burnout

Engineering Contradiction:
Improvelayout sizeVSAvoidESD current concentration
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The doping region with third conductivity type creates localized P/N junctions at strategic positions, generating non-uniform electric fields that redirect and distribute ESD current more evenly across multiple MOS transistor fingers. This prevents current concentration on specific transistors while maintaining the compact multi-finger layout, thereby reducing the harmful effect of ESD current concentration

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures uniform turn-on of MOS transistors, preventing overload and burnout by increasing substrate bias and allowing simultaneous discharge of ESD current, while maintaining a compact layout size.

Implementation Method 1

the concentrations of the doping region and the source/drain of the MOS transistor are substantially greater than that of the doping well. The reverse breakdown voltage of the P/N junction interface could be small enough to be ignored. When the parasitic BJT circuit of the MOS transistor is triggered by high-voltage, the ESD current that is directed into the MOS transistor through the input (or output) pad may drive the charge carriers, such as free electrons and holes, coming from the base of the parasitic BJT tunneling through the P/N junction interface.

Methodology Applied
Scientific EffectTunneling:

Data Source

PatentUS10181466B2Electrostatic discharge protection apparatus and applications thereof
Publication Date: 2019.01.15 MACRONIX INTERNATIONAL CO LTD
  • US10181466B2 patent drawing
  • US10181466B2 patent drawing
  • US10181466B2 patent drawing

AI summary

An ESD protection apparatus includes a semiconductor substrate, a first gate structure, a first doping region, a second doping region and a third doping region. The semiconductor substrate has a doping well with a first conductivity one end of which is grounded. The first gate structure is disposed on the doping well. The first doping region having a second conductivity, is disposed in the doping well and adjacent to the first gate structure, and is electrically connected to a pad. The second doping region having the second conductivity is disposed in the doping well and adjacent to the first gate structure. The third doping region having the first conductivity is disposed in the doping well and forms a P/N junction interface with the second doping region, wherein the second doping region and the third doping region respectively have a doping concentration substantially greater than that of the doping well.