ESD Protection Device Using Vertical Stacked Bipolar Transistor

Solution Overview

Problem

Conventional ESD protection devices face challenges in achieving high device density with low parasitic resistance when turned on and good noise isolation when turned off, which is essential for semiconductor devices to prevent electrostatic discharge damage.

Innovation Solution

The ESD protection device employs a parasitic PNP or NPN bipolar transistor structure with doped regions and wells of opposite conductive types, coupled to power supply or ground terminals, to provide an efficient ESD path and noise isolation by reducing parasitic resistance and increasing current injection capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the well area is increased to reduce the parasitic resistance of the conventional power cut cell, then the parasitic resistance is reduced, but the total device area increases

Engineering Contradiction:

Improveparasitic resistanceVSAvoidtotal device area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a two-dimensional planar diode structure to a three-dimensional vertically stacked structure. The ESD protection device is formed by stacking multiple layers (first semiconductor layer, second semiconductor layer, third semiconductor layer) vertically, allowing the current path to extend in the vertical dimension rather than requiring lateral expansion. This dimensional change enables reduced parasitic resistance without increasing the lateral device footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where the ESD protection device is integrated within the existing semiconductor device architecture. The first, second, and third semiconductor layers are stacked and integrated with the main device structure, with conductive layers and insulating layers nested between them. This nesting allows the ESD protection functionality to be embedded within the vertical stack rather than occupying additional lateral space.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Reliability

If MOS transistors are used to transmit larger ESD transient current by reducing output impedance, then the ESD current transmission capability is improved, but the total device area increases

Engineering Contradiction:

ImproveESD current transmission capabilityVSAvoidtotal device area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent replaces the conventional MOS transistor-based ESD protection mechanism with a vertically stacked semiconductor structure that utilizes field effect and carrier injection mechanisms. Instead of relying on MOS transistor channels that require lateral gate structures, the invention uses a vertical stack with doped regions and conductive layers that can handle high ESD currents through the vertical current path, eliminating the need for large lateral MOS transistor structures.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent transitions from a two-dimensional planar MOS transistor structure to a three-dimensional vertically stacked structure. The ESD protection device is formed by stacking multiple layers (first semiconductor layer, second semiconductor layer, third semiconductor layer) vertically, allowing the current path to extend in the vertical dimension rather than requiring lateral expansion. This dimensional change enables reduced parasitic resistance without increasing the lateral device footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables effective transmission of ESD transient currents with reduced voltage difference between circuits, while maintaining noise isolation efficiency and supporting high device density without increasing the total device area.

Implementation Method 1

The ESD protection device employs a parasitic PNP or NPN bipolar transistor structure with doped regions and wells of opposite conductive types, coupled to power supply or ground terminals, to provide an efficient ESD path and noise isolation by reducing parasitic resistance and increasing current injection capacity.

Methodology Applied

Scientific EffectParasitic bipolar transistor effect:

Implementation Method 2

This configuration enables effective transmission of ESD transient currents with reduced voltage difference between circuits, while maintaining noise isolation efficiency and supporting high device density without increasing the total device area.

Methodology Applied

Scientific EffectNoise isolation:

Data Source

PatentUS8217494B2Electrostatic discharge protection device

Publication Date: 2012.07.10 SILICON MOTION INC

AI summary

The invention provides an electrostatic discharge (ESD) protection device having an ESD path between a first circuit and a second circuit. The electrostatic discharge protection device includes a first doped region having a first conductive type. A first well has a second conductive type opposite to the first conductive type. A second doped region and a third doped region are in the first well, respectively having the first and second conductive types. The first doped region is coupled to a power supply terminal or a ground terminal of the first circuit, and the second and third doped regions are both coupled to a power supply terminal or a ground terminal of the second circuit, respectively.