ESD Protection Circuit with Voltage Divider and Detection Logic

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Solution Overview

Problem

As transistors in integrated circuits shrink, they become more susceptible to damage from electrostatic discharge (ESD) due to lower withstanding voltages, and existing ESD protection circuits may not effectively manage voltage differences between terminals, leading to potential damage from over-voltage stress.

Innovation Solution

An ESD protection device comprising a voltage divider circuit, a detector circuit, and a clamping circuit that generates control signals to activate a discharging path when an ESD event occurs, maintaining voltage levels within safe limits by using resistive and capacitive components, and inverters or multiplexers to manage voltage differences between power rails.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If transistor size is reduced to improve integration density, then manufacturing precision and productivity are improved, but the voltage withstanding capability deteriorates, making the circuit more susceptible to ESD damage

Engineering Contradiction:
Improveintegration densityVSAvoidvoltage withstanding capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces an intermediary ESD protection circuit between the power rails and the transistor to handle voltage stress. This intermediary structure includes detection units that monitor voltage differences and activation units that provide protective current paths, allowing the transistor to operate at higher densities while the protection circuit manages the voltage withstanding requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conventional ESD protection circuits are used, then some level of protection is provided, but they fail to effectively manage voltage differences between terminals, leading to potential damage

Engineering Contradiction:
ImproveESD protectionVSAvoidvoltage difference management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The ESD protection circuit is segmented into multiple functional units: detection units (first and second detection units) that monitor different voltage differences, and activation units that independently control protective paths. This segmentation allows precise management of voltage differences between specific terminals without requiring a monolithic complex structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The detection units continuously monitor voltage differences between power rails and generate control signals based on detected anomalies. This feedback mechanism enables the activation units to dynamically adjust protective current paths only when voltage stress is detected, providing effective protection while maintaining normal circuit operation without unnecessary intervention.

Inventive Principle:
Principle #23Feedback

3Stability of the object's composition

If voltage divider circuit is used to generate bias voltages, then voltage levels are stabilized, but additional circuit components increase device complexity

Engineering Contradiction:
Improvevoltage level stabilityVSAvoidcircuit components
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The voltage divider circuit serves multiple functions: it generates bias voltages for transistor operation, establishes reference voltage levels for the detection units, and provides a stable voltage foundation for the entire ESD protection circuit. This multi-functionality reduces the need for separate voltage generation circuits, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces transient voltages introduced by ESD events, enhancing the reliability of internal components by preventing excessive voltage drops between terminals and providing a controlled discharging path, thus protecting the integrated circuit from over-voltage damage.

Implementation Method 1

a voltage divider circuit coupled between a first power rail and a second power rail, the voltage divider circuit outputting a first bias voltage and a second bias voltage

Methodology Applied
Scientific EffectVoltage division: Electrical Resistance

Implementation Method 2

a detector circuit coupled to the voltage divider circuit and the first power rail and the second power rail, the detector circuit generating at least N control signals according to the N−1 bias voltages and the voltages VDDH and VSS

Methodology Applied
Scientific EffectVoltage detection: Electric Field

Implementation Method 3

a clamping circuit coupled between the first power rail and the second power rail, the clamping circuit being configured to be turned on according to the at least N control signals VC1-VCN, in order to provide a discharging path for a current IESD associated with the ESD event

Methodology Applied
Scientific EffectElectrostatic discharge: Electrostatic Discharge

Data Source

PatentUS11146060B2Electrostatic discharge protection device and electrostatic discharge detector circuit
Publication Date: 2021.10.12 REALTEK SEMICON CORP
  • US11146060B2 patent drawing
  • US11146060B2 patent drawing
  • US11146060B2 patent drawing

AI summary

An electrostatic discharge (ESD) protection device includes a voltage divider circuit, a detection circuit, and a clamping circuit. The voltage divider circuit outputs N−1 bias voltages according to a first voltage and a second voltage, in which N is a positive integer greater than or equal to 2. The detection circuit detects an ESD event according to a voltage level at a predetermined node associated with the first voltage and the second voltage, and to generate N control signals according to the first voltage, the second voltage, and the N−1 bias voltages. When the ESD event occurs, the voltage level of the N control signals are the same as the first voltage. The clamping circuit is turned on according to the N control signals when the ESD event occurs, in order to provide a discharging path of a current associated with the ESD event.