ESD Protective Element With Floating Regions For High-Voltage SOI
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional ESD protective elements for high-voltage semiconductor integrated circuits with a silicon-on-insulator (SOI) structure face challenges in increasing breakdown voltage and ESD tolerance without significantly increasing chip area or manufacturing cost, as they are prone to thermal destruction and require larger sizes to achieve sufficient reverse breakdown voltage.
Innovation Solution
The ESD protective element is designed with a semiconductor layer having regions of different conduction types with varying impurity concentrations, where the second semiconductor region has a higher impurity concentration, allowing for increased breakdown and trigger voltages, and is electrically floating to enhance current stand-up slope and snap-back current, enabling sharing among multiple unit circuit cells to reduce the number of ESD protective elements required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of ESD protective element is increased to achieve sufficient reverse breakdown voltage, then ESD tolerance is improved, but chip area increases
Solution Approach 1:
The patent applies local quality by creating semiconductor regions with different impurity concentrations in specific locations. The first semiconductor region has a first impurity concentration while the second semiconductor region has a second impurity concentration that is 1×10^18 to 1×10^20 times higher. This localized variation in impurity concentration allows the ESD protective element to achieve high breakdown voltage and ESD tolerance without requiring a large overall device area, thus resolving the contradiction between reliability and chip area.
2Reliability
If the breakdown voltage is increased to match high-voltage semiconductor integrated circuits, then ESD tolerance is improved, but the number of ESD protective elements required increases
Solution Approach 1:
The patent employs parameter changes by systematically varying the impurity concentration parameter across different semiconductor regions. The first semiconductor region maintains a base impurity concentration while the second semiconductor region has an impurity concentration 1×10^18 to 1×10^20 times higher. This parameter variation enables a single ESD protective element to handle high-voltage applications with sufficient ESD tolerance, reducing the total number of protective elements needed and improving productivity.
3Reliability
If the impurity concentration is increased to increase breakdown voltage, then ESD tolerance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements local quality by confining the high impurity concentration to specific semiconductor regions rather than uniformly across the entire device. The second semiconductor region, with its elevated impurity concentration (1×10^18 to 1×10^20 times the first region), is localized to where it is most needed for breakdown voltage control. This spatial localization of quality variation simplifies manufacturing precision requirements compared to uniform high-precision control across the entire device.
Solution Approach 2:
The patent applies preliminary action by pre-establishing the impurity concentration gradient during the manufacturing process. The first semiconductor region is formed with a base impurity concentration, and subsequently the second semiconductor region is created with significantly higher impurity concentration through targeted doping processes. This preliminary establishment of the concentration gradient before final device assembly simplifies subsequent manufacturing steps and reduces overall precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively increases breakdown and trigger voltages to match high-voltage semiconductor integrated circuits, reduces the number of ESD protective elements needed, and minimizes chip area and manufacturing costs by allowing a larger current capacity without increasing voltage significantly, thus providing enhanced ESD tolerance and cost-effectiveness.
Implementation Method 1
a first semiconductor region of a first conduction type formed in the semiconductor layer, a first semiconductor region of a second conduction type formed in the semiconductor layer in proximity or next to the first semiconductor region of the first conduction type
Implementation Method 2
The impurity concentration in the second semiconductor region of the second conduction type is higher than the impurity concentration in the first semiconductor region of the second conduction type
Implementation Method 3
the first semiconductor region of the second conduction type and the second semiconductor region of the second conduction type are set electrically floating
Data Source
AI summary
The present invention mainly provides an ESD protective element which can be built in high voltage semiconductor integrated circuit devices without increasing the chip area. An ESD protective element according to one embodiment has a construction comprising a semiconductor layer, a first region of a first conduction type formed in the semiconductor layer, a first region of a second conduction type formed in the semiconductor layer away from the first region of the first conduction type, a second region of the second conduction type formed in the first region of the second conduction type and has a higher impurity concentration than it, and a second region of the first conduction type formed in the second region of the second conduction type and has a high impurity concentration. The first and second regions of the second conduction type are in an electrically floating state.