ESD Pulse Detection Circuit for False-Start-Free Charge Discharge
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Solution Overview
Problem
Integrated circuit designs face challenges in electro-static discharge (ESD) protection, especially at narrower line widths, where existing ESD protection circuits struggle to accurately distinguish between normal power-on and ESD events, leading to false starts and incomplete discharge of electro-static charges.
Innovation Solution
An ESD protection circuit incorporating an ESD transistor and an electro-static pulse detection circuit with a capacitor and resistor or diode group, which detects pulses to differentiate between normal and ESD events, prolongs discharge time, and reduces layout space and leakage current, ensuring effective ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing ESD protection circuits are used, then ESD protection is provided, but the circuit cannot accurately distinguish between normal power-on and ESD events, leading to false starts
Solution Approach 1:
The patent implements a feedback mechanism where the detection circuit monitors the voltage change rate and provides feedback control to distinguish between normal power-on and ESD events. The circuit uses the voltage change characteristics as feedback signals to activate or deactivate the ESD protection transistor accordingly, resolving the contradiction between detection accuracy and false start rate.
Solution Approach 2:
The patent introduces dynamic detection by monitoring the voltage change rate (dV/dt) rather than using static voltage thresholds. The ESD protection circuit dynamically adjusts its activation state based on the real-time voltage change characteristics, enabling accurate differentiation between normal power-on (slow voltage rise) and ESD events (rapid voltage spike).
2Reliability
If ESD protection circuit is activated to discharge electro-static charges quickly, then protection effectiveness is improved, but discharge time may be insufficient and layout space increases
Solution Approach 1:
The patent employs dynamic control of the ESD transistor based on real-time voltage change rate detection. When an ESD event is detected (rapid voltage rise), the transistor is immediately activated to provide fast discharge path. The circuit dynamically adjusts the discharge duration based on the actual ESD event characteristics, achieving both fast discharge and appropriate discharge time without excessive layout space.
3Area of stationary object
If ESD protection circuit components are reduced to minimize layout space, then area is reduced, but detection capability and charge discharge completeness may be compromised
Solution Approach 1:
The patent designs the ESD transistor to serve multiple functions: it acts as both the protection element and the discharge path. The detection circuit is integrated with the protection transistor, sharing control nodes and substrate connections. This multi-functional design achieves effective ESD protection and complete charge discharge with minimized layout space.
Solution Approach 2:
The patent merges the detection circuit and protection transistor into a tightly integrated structure where the output terminal of the detection circuit is electrically connected to both the control terminal and substrate end of the ESD transistor. This merging of detection and protection functions into a unified circuit structure reduces overall layout space while maintaining complete charge discharge capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents damage from electro-static discharges by fully discharging charges quickly and reducing false starts, while minimizing layout space and leakage current, thereby enhancing the reliability of semiconductor devices.
Implementation Method 1
electro-static discharge (ESD) protection
Data Source
AI summary
An electro-static discharge (ESD) protection circuit is electrically connected to a first pad and a second pad. The ESD protection circuit includes an ESD transistor having a control terminal, a first terminal electrically connected to the first pad, a second terminal electrically connected to the second pad, and a substrate end; and an electro-static pulse detection circuit having an upper terminal electrically connected to the first pad, a lower terminal electrically connected to the second pad, and an output terminal electrically connected to the control terminal and the substrate end of the ESD transistor.