ESD-Resistant Integrated Circuit with Schottky Barrier Drain
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Solution Overview
Problem
Integrated circuits, particularly those with high voltage transistors, are vulnerable to damage from electrostatic discharge (ESD) events, and existing protection methods have limitations in preventing damage from sudden electrical flows.
Innovation Solution
The integration of a heavily doped source area and a lightly doped drain area with conductivity determining impurities, where the drain conductor directly contacts the lightly doped drain area, forming a Schottky barrier that separates the drain conductor from the channel, and a gate overlies the channel, creating an ambipolar structure capable of withstanding higher electrical currents and voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor structures with heavily doped drain areas are used, then manufacturing is easier and standard fabrication processes can be applied, but the transistors are highly susceptible to electrostatic discharge damage and voltage spikes
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping profile in the drain region, with a lightly doped portion adjacent to the channel and a heavily doped portion away from the channel. This localized variation in doping concentration provides ESD protection where needed (near the channel) while maintaining standard heavy doping elsewhere for normal operation, thus improving reliability without uniformly increasing device complexity throughout the entire transistor structure.
Solution Approach 2:
The lightly doped drain portion acts as an intermediary element between the channel and the heavily doped drain region. This intermediate structure with moderate doping concentration serves as a buffer that protects the channel from high electric fields during ESD events, while still allowing normal current flow during operation. The intermediary structure resolves the contradiction by providing protection without requiring complete restructuring of the drain region.
2Reliability
If lightly doped drain areas with direct drain conductor contact are implemented, then transistors can withstand over 100 times the current of prior art before breakdown, but manufacturing precision requirements increase due to specific doping concentration ranges
Solution Approach 1:
The patent employs parameter changes by specifying precise doping concentration ranges for different drain regions (lightly doped portion with lower concentration, heavily doped portion with higher concentration). These controlled parameter variations enable the transistor to achieve enhanced ESD protection capability while providing clear fabrication guidelines that balance manufacturing precision requirements with performance benefits.
Solution Approach 2:
The patent applies partial action by implementing light doping in only a portion of the drain region (the portion adjacent to the channel) rather than throughout the entire drain. This partial modification provides sufficient ESD protection without requiring complete restructuring of the drain, thereby reducing overall manufacturing precision requirements compared to uniform heavy modifications throughout the entire drain region.
3Power
If heavily doped source and drain areas are used for high current capability, then transistors can handle higher amperage, but they become more vulnerable to electrostatic discharge damage
Solution Approach 1:
The patent resolves this contradiction by applying local quality through spatially varying doping concentrations in the drain region. The lightly doped portion near the channel provides ESD protection, while the heavily doped portion away from the channel maintains high current handling capability. This localized differentiation allows the transistor to simultaneously achieve both power handling and ESD resistance without compromising either property.
Solution Approach 2:
The drain region is segmented into distinct doping zones: a lightly doped portion adjacent to the channel and a heavily doped portion away from the channel. This segmentation allows each zone to perform its specific function - the lightly doped zone protects against ESD while the heavily doped zone handles high current - thereby resolving the contradiction between power capability and ESD susceptibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables integrated circuits to withstand significantly higher amperage and voltage before breakdown, making them more resistant to electrostatic discharge damage, with some embodiments capable of withstanding over 100 times the current of prior art transistors before breakdown.
Implementation Method 1
forming a Schottky barrier that separates the drain conductor from the channel
Implementation Method 2
implanting conductivity determining impurities into a substrate at a concentration of from about 1×10^14 to about 1×10^15 per cubic centimeter to form a lightly doped drain area
Data Source
AI summary
Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a heavily doped source area having conductivity determining impurities at a heavily doped source concentration and a lightly doped drain area having conductivity determining impurities at a lightly doped drain concentration less than the heavily doped source concentration. A drain conductor directly contacts the lightly doped drain area, and a channel is positioned between the heavily doped source area and the lightly doped drain area. A gate overlies the channel.