ESD Routing Paths in SoC Package Substrates
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Solution Overview
Problem
Conventional electrostatic discharge (ESD) protection methods for system on chip (SoC) are inadequate as they cannot be modified during operation and fail to effectively manage noise coupling between RF and digital circuitry, making integrated circuits susceptible to damage from ESD events.
Innovation Solution
A system and method that routes ESD current via low impedance DC paths and high impedance AC paths within the IC package, electrically coupling RF and digital ground planes to mitigate noise and potential differences, while allowing for configuration based on frequency and tolerable resistance and inductance to prevent damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection methods are used, then the IC is protected from electrostatic discharge, but the protection device cannot be modified during operation and occupies additional space outside the IC
Solution Approach 1:
The patent implements dynamic ESD protection by incorporating switchable paths that can be configured during operation. Multiple ESD paths are provided with switches that allow selective activation based on operational conditions, enabling the protection mechanism to adapt dynamically rather than being fixed in a static configuration.
Solution Approach 2:
The ESD protection structure is integrated within the IC package itself, serving multiple functions: ESD protection, noise isolation between RF and digital circuitry, and configurable adaptability. The same integrated structure provides both protection and isolation functions that would otherwise require separate components.
2Ease of manufacture
If ESD protection is integrated within the IC package, then space is saved and cost is reduced, but the protection must be fixed and cannot be adjusted during operation
Solution Approach 1:
The integrated ESD protection structure incorporates switchable elements that enable dynamic configuration during operation. Multiple ESD paths with associated switches allow the system to adapt the protection characteristics based on operational requirements, maintaining configurability despite the integrated fixed-structure approach.
Solution Approach 2:
The ESD protection is divided into multiple separate paths within the integrated structure, each with its own switchable elements. This segmentation allows selective activation of different protection paths based on operational conditions, providing configurability within the integrated package.
3Object-generated harmful factors
If RF and digital ground planes are electrically coupled, then noise isolation is improved, but the ESD current path may pass through sensitive IC circuitry causing damage
Solution Approach 1:
The ESD current path is extracted and routed outside the IC through the package substrate, separating the high-current ESD discharge path from the sensitive on-chip circuitry. This allows the ground planes to be coupled for noise isolation while ESD currents bypass the sensitive elements through the package external path.
Solution Approach 2:
The package substrate serves as an intermediary medium that provides both the ESD current path and the ground plane coupling. The substrate acts as a mediator that allows electrical coupling for noise isolation while providing a dedicated low-impedance path for ESD currents that does not pass through sensitive IC circuitry.
4Reliability
If ESD paths have low impedance at DC, then ESD current diversion is effective, but the paths may couple noise at RF frequencies utilized in the IC
Solution Approach 1:
The ESD paths are designed with different impedance characteristics at different frequencies: low impedance at DC for effective ESD current diversion, and high impedance at RF frequencies to prevent noise coupling. This frequency-dependent impedance characteristic is achieved through specific path geometries and configurations in the package substrate.
Solution Approach 2:
The impedance of the ESD paths is engineered to change with frequency. The paths exhibit low impedance at DC to effectively divert ESD currents, while presenting high impedance at RF frequencies to prevent noise coupling. This parameter change with frequency is achieved through the physical configuration and dimensions of the paths in the package substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces the risk of ESD damage by diverting large currents away from the IC and improving noise isolation between RF and digital circuitry, while being cost-effective and space-efficient by fabricating the connections in the IC package rather than on-chip or as external components.
Implementation Method 1
ESD current may be routed via one or more paths within and/or on a package to which the IC is bonded
Implementation Method 2
The one or more paths may have low impedance at DC
Implementation Method 3
The one or more paths may have high impedance at one or more frequencies utilized in the IC
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Aspects of a method and system for mitigating risk of electrostatic discharge in a system on chip (SoC) are provided. In this regard, for an IC (142) comprising a plurality of portions (124,126) electrically isolated from one another within the IC, ESD current may be routed via one or more paths (146) within and/or on a package (144) to which the IC is bonded. The one or more paths may electrically couple two or more of the portions of the IC. The one or more paths may have low impedance at DC and high impedance at one or more frequencies utilized in the integrated circuit. One of the portions (124) of the IC may be a ground plane for RF circuitry. One of the portions (126) of the IC may be a ground plane for digital circuitry. The one or more paths may be fabricated in one or more metal layers of said package.