ESD Protection Structure With Segmented Emitters for Higher Holding Voltage

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Solution Overview

Problem

Existing electrostatic discharge (ESD) protection structures for integrated circuits face challenges in effectively reducing emitter injection efficiency and enhancing holding voltage to prevent damage from transient ESD power.

Innovation Solution

The proposed electrostatic discharge protection structure incorporates doped regions of different conductivity types connected with doped regions used as emitters of bipolar junction transistors (BJTs) to reduce emitter injection efficiency and enhance holding voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional ESD protection structures are used, then basic ESD protection is provided, but emitter injection efficiency cannot be effectively reduced and holding voltage cannot be enhanced

Engineering Contradiction:
ImproveESD protection effectivenessVSAvoiddoped region configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The emitter region is segmented into multiple doped regions (first doped region, second doped region, third doped region, fourth doped region) with different conductivity types arranged in a specific pattern. This segmentation allows independent control of injection efficiency while maintaining protection function, resolving the contradiction between reliability improvement and device complexity by dividing the emitter into functional segments rather than using a uniform structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different doped regions are assigned different conductivity types (n-type and p-type) and doping concentrations to create local variations in electrical properties. The first and third doped regions have one conductivity type while the second and fourth have another, creating localized zones with optimized injection characteristics. This local quality differentiation enables reduced emitter injection efficiency in specific areas while maintaining overall ESD protection reliability

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If doped regions of different conductivity types are added to reduce emitter injection efficiency, then holding voltage is enhanced, but device complexity increases

Engineering Contradiction:
Improveemitter injection efficiencyVSAvoiddoped region structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

Multiple doped regions with different conductivity types are merged into a single integrated emitter structure that functions as one bipolar junction transistor emitter. The first, second, third, and fourth doped regions are combined to form a unified emitter configuration that simultaneously achieves reduced injection efficiency and enhanced holding voltage without requiring separate discrete components, thus managing device complexity through functional integration

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The emitter structure uses composite doping configuration combining n-type and p-type doped regions in a specific arrangement. This composite structure of oppositely doped regions creates the desired electrical characteristics (reduced injection efficiency and enhanced holding voltage) while maintaining a single integrated emitter entity, balancing performance improvement with acceptable device complexity

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS20250120185A1Electrostatic discharge protection structure
Publication Date: 2025.04.10 UNITED MICROELECTRONICS CORP
  • US20250120185A1 patent drawing
  • US20250120185A1 patent drawing
  • US20250120185A1 patent drawing

AI summary

An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.