Low-Capacitance ESD Device Segmented Finger Design

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Solution Overview

Problem

Integrated circuit layouts face challenges in optimizing electrostatic discharge (ESD) devices for high-speed circuitry, particularly in reducing the resistance-capacitance (RC) product to minimize noise and ensure effective ESD protection without compromising circuit performance.

Innovation Solution

A low-capacitance ESD device design is implemented, featuring a single active region with multiple active lines and reduced pick-up lines, which decreases capacitance while maintaining or improving breakdown current, allowing for effective ESD protection in high-speed circuits by decoupling design objectives for front-end and back-end circuit elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional ESD device design is used, then ESD protection is provided, but capacitance and RC product increase causing noise in high-speed circuitry

Engineering Contradiction:
ImproveESD protectionVSAvoidnoise
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The ESD device is segmented into multiple fingers (typically 4-16 fingers) arranged in parallel, each finger providing independent ESD protection pathways. This segmentation reduces the total capacitance by distributing the protection function across multiple smaller units rather than a single large structure, thereby reducing noise in high-speed circuitry while maintaining ESD protection capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar ESD device design to a three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change increases the effective surface area for ESD protection without proportionally increasing the footprint capacitance, as the vertical fins provide additional protection pathways in the third dimension while minimizing capacitive coupling to adjacent circuit elements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If ESD device size is increased to improve protection, then breakdown current increases, but capacitance and RC product increase causing noise

Engineering Contradiction:
Improvebreakdown currentVSAvoidRC product
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The ESD device divides the total breakdown current requirement into multiple parallel finger structures, each contributing a portion of the total current. This segmentation allows the device to achieve high total breakdown current (e.g., 10A or more) while each individual finger maintains low capacitance, thereby keeping the overall RC product low and minimizing noise.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs a composite structure combining n-type and p-type doped regions in alternating finger patterns, creating a complementary ESD protection mechanism. This composite design leverages the different electrical characteristics of n-type and p-type materials to optimize both breakdown current and capacitance properties, achieving high protection capability with minimized RC product.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS10109621B2Low-capacitance electrostatic damage protection device and method of designing and making same
Publication Date: 2018.10.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10109621B2 patent drawing
  • US10109621B2 patent drawing
  • US10109621B2 patent drawing

AI summary

An electrostatic discharge (ESD) device includes an active region. The active region includes a first active line having a first plurality of gate features; and a second active line having a second plurality of gate features. The ESD device further includes a first pick-up line having a third plurality of gate features, wherein the first active line is between the first pick-up line and the second active line. The ESD device further includes a second pick-up line comprising a fourth plurality of gate features, wherein the second active line is between the second pick-up line and the first active line.