ESD Protection Apparatus with Segmented Junctions
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Solution Overview
Problem
Parasitic silicon controlled rectifiers (SCRs) in ESD protection circuits have a holding voltage lower than their trigger voltage, leading to electrical overstress (EOS) and latch-up risks during normal operation.
Innovation Solution
An ESD protection apparatus with a semiconductor substrate, multiple doping regions of different conductivities, and junctions formed between them, which increases the effective resistance and holding voltage, thereby moderating the EOS and latch-up risk by lengthening the current path through P+/N+ junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a parasitic SCR is used in ESD protection circuits, then the current sinking/sourcing capability and heat dissipation are improved, but the holding voltage becomes far less than the trigger voltage, causing EOS or latch-up risk
Solution Approach 1:
The patent segments the SCR structure by introducing additional doping regions (first and second doping regions with first conductivity, third and fourth doping regions with second conductivity) that form multiple junctions within the SCR. This segmentation creates intermediate potential barriers that increase the holding voltage while maintaining the overall SCR functionality for current sinking and heat dissipation.
Solution Approach 2:
The patent applies local quality by creating regions with different conductivity types (first conductivity and second conductivity) at specific locations within the SCR structure. The doping regions are strategically positioned to form junctions with specific electrical characteristics that locally increase the holding voltage without compromising the overall power handling capability.
2Power
If a parasitic SCR is used in ESD protection circuits, then the turn-on impedance is very low, but the holding voltage is far less than the trigger voltage, leading to electrical overstress risk
Solution Approach 1:
The SCR is segmented into multiple regions with different conductivity types, creating several junctions between them. This segmentation allows the structure to maintain low turn-on impedance for ESD protection while introducing intermediate potential barriers that raise the holding voltage above the trigger voltage, preventing electrical overstress during normal operation.
Solution Approach 2:
The additional doping regions act as intermediary elements between the anode and cathode of the SCR. These intermediary regions form junctions that create potential barriers, effectively mediating the voltage distribution and ensuring that the holding voltage exceeds the trigger voltage, thereby preventing harmful electrical overstress.
3Reliability
If the holding voltage is increased above the trigger voltage, then the EOS and latch-up risk are reduced, but the structure complexity increases with multiple doping regions and junctions
Solution Approach 1:
The patent merges the ESD protection function with the voltage control function by integrating multiple doping regions and junctions directly into the SCR structure. This combining approach increases reliability by raising the holding voltage above the trigger voltage while avoiding the need for separate control circuits, thus managing the complexity through functional integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the holding voltage of the parasitic SCR, reducing the risk of electrical overstress and latch-up, and improving the overall performance of the ESD protection apparatus.
Implementation Method 1
at least one junction formed by different conductivities is formed by the first doping region and the second doping region, or formed by the third doping region and the fourth doping region
Data Source
AI summary
An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region, a fourth doping region and at least one junction formed by different conductivities. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in the semiconductor substrate. The first doping region having the first conductivity is disposed in the first well. The second doping region having the second conductivity is disposed in the first well. The third doping region and the fourth doping region respectively having the first conductivity and the second conductivity are disposed in the second well. The at least one junction is formed by the first doping region and the second doping region, or formed by the third doping region and the fourth doping region.