Electrostatic Discharge Structure for Semiconductor Package

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Solution Overview

Problem

During the die attach process in semiconductor package manufacturing, highly electrostatic charges are generated, which can damage logic chips due to insufficient electrostatic discharge management by existing ionizer systems.

Innovation Solution

An electrostatic discharge structure is formed on a ground substrate pad between semiconductor devices, allowing safe discharge of electrostatic charges through a grounded path, preventing damage to the first semiconductor device and improving product yield and productivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If an ionizer is used to remove electrostatic charges during the die attach process, then electrostatic charge removal is attempted, but the capability is insufficient and management is difficult, causing damage to logic chips

Engineering Contradiction:
Improveelectrostatic charge damageVSAvoidlogic chip integrity
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The harmful electrostatic charges are extracted and directed to a specific discharge path through the electrostatic discharge structure. The structure includes a discharge electrode that extracts charges from the adhesive film peeling process and guides them to a ground substrate pad, separating the charge dissipation function from the chip operation area.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The electrostatic discharge structure acts as an intermediary between the adhesive film and the logic chip. It provides a controlled path for electrostatic charges generated during adhesive film peeling, preventing direct discharge onto the chip while safely directing charges to ground through the substrate pad.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If multiple semiconductor chips are stacked on a package substrate, then device functionality is improved, but electrostatic charges generated during die attach process increase the risk of damage

Engineering Contradiction:
Improvesemiconductor package functionalityVSAvoidelectrostatic charge accumulation
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The electrostatic discharge structure is prepared in advance on the package substrate before the die attach process begins. The discharge electrode and ground substrate pad are pre-positioned to ensure that when multiple chips are stacked and adhesive films are peeled, charges have an immediate safe path available.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The harmful electrostatic charges generated during the die attach process of stacked chips are converted into a beneficial controlled discharge through the electrostatic discharge structure. Instead of allowing random discharge that could damage chips, the structure channels charges through a designated path to ground, transforming a harmful byproduct into a controlled process feature.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The electrostatic discharge structure effectively manages electrostatic charges, preventing damage to the first semiconductor device and enhancing the yield and productivity of semiconductor packages by ensuring safe discharge during the die attach process.

Implementation Method 1

highly electrostatic charges may be generated when an adhesive film peels off from an underlying based film

Methodology Applied
Scientific EffectElectrostatic discharge: Electrostatic Discharge

Implementation Method 2

forming an electrostatic discharge structure on a ground substrate pad exposed from an upper surface of the package substrate

Methodology Applied
Scientific EffectGrounding: Earthing

Data Source

PatentUS11594500B2Semiconductor package
Publication Date: 2023.02.28 SAMSUNG ELECTRONICS CO LTD
  • US11594500B2 patent drawing
  • US11594500B2 patent drawing
  • US11594500B2 patent drawing

AI summary

In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.