ESD Protection Semiconductor Device with Segmented Charge Injection

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Solution Overview

Problem

Existing electrostatic discharge (ESD) protection devices face a trade-off between parasitic capacitance and transient overvoltage, where reducing the distance between anode and cathode to prevent overvoltage increases capacitance, detrimental in high-speed applications.

Innovation Solution

The semiconductor device incorporates a first structure with a third and fourth semiconductor region of alternate charge types, connected by a first connection element, allowing an indirect current path during ESD events, reducing overvoltage while maintaining low capacitance by injecting charge carriers from these regions, enabling faster switching and reduced capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If the distance between anode and cathode is reduced to prevent transient overvoltage, then the overvoltage is limited, but the parasitic capacitance increases

Engineering Contradiction:
Improvetransient overvoltageVSAvoidparasitic capacitance
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The semiconductor body is divided into multiple regions (first, second, third, and fourth regions) with alternating charge types, creating a segmented structure that enables multiple current paths. This segmentation allows charge carriers to be injected from intermediate regions, reducing overvoltage without requiring the anode and cathode to be closely spaced, thereby avoiding increased parasitic capacitance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The third and fourth semiconductor regions act as intermediary structures between the anode (first region) and cathode (second region). These intermediate regions provide additional charge carrier injection points that facilitate faster switching and reduce transient overvoltage without requiring direct close spacing between anode and cathode, thus maintaining low parasitic capacitance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If the distance between anode and cathode is reduced to enable faster charge carrier flooding, then the switching speed improves, but the capacitance increases which degrades high-speed application performance

Engineering Contradiction:
Improveswitching speedVSAvoidparasitic capacitance
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The semiconductor body is segmented into multiple regions with alternating charge types, creating a multi-region structure that enables distributed charge carrier injection. This segmentation allows the device to achieve fast switching by injecting carriers from intermediate regions without requiring the anode and cathode to be closely spaced, thereby avoiding increased parasitic capacitance that would degrade high-speed performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention extends the charge carrier injection process into additional spatial dimensions by introducing third and fourth regions that are positioned between the anode and cathode. This dimensional expansion provides multiple injection pathways and intermediate injection points, enabling faster switching without constraining the anode-cathode distance and thus maintaining low parasitic capacitance for high-speed applications.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively limits overvoltage during ESD events with minimal impact on capacitance, enhancing the performance of ESD protection devices in high-speed applications by allowing charge carriers to be injected from intermediate regions, thus reducing the duration and magnitude of transient overvoltage.

Implementation Method 1

a third semiconductor region 6A of the second charge type, a fourth semiconductor region 6B of the first charge type, and a first connection element 7 configured to electrically connect the third semiconductor region to the fourth semiconductor region... allowing charge carriers to be injected from intermediate regions

Methodology Applied
Scientific EffectCharge carrier injection: Conduction (electrical)

Data Source

PatentEP4068357A1Semiconductor device and ESD protection device comprising the same
Publication Date: 2022.10.05 NEXPERIA BV
  • EP4068357A1 patent drawingFigure 1
  • EP4068357A1 patent drawingFigure 2~3A
  • EP4068357A1 patent drawingFigure 3B

AI summary

The present invention relates to an electrostatic discharge protection device. More in particular, the present invention relates to a semiconductor device that is particularly suitable as a component for electrostatic discharge protection. The semiconductor device is characterized in that it comprises a first structure, comprising: a third semiconductor region of the second charge type, a fourth semiconductor region of the first charge type and being spaced apart from the third semiconductor region, and a first connection element configured to electrically connect the third semiconductor region to the fourth semiconductor region, wherein the third semiconductor region is arranged in between the first semiconductor region and the fourth semiconductor region, and wherein the fourth semiconductor region is arranged in between the second semiconductor region and the third semiconductor region.