Electrostatic Shielding Pattern for Array Substrate ESD Protection
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Solution Overview
Problem
The increasing complexity of display panels with narrower bezels poses a challenge in effectively isolating test lines during anti-electrostatic testing, leading to potential damage from electrostatic discharge (ESD) due to insufficient margin for configuring test lines far from the testing region.
Innovation Solution
An array substrate is designed with an electrostatic shielding pattern, including a main portion and an electrostatic out-guiding portion, disposed over the test line and insulated by an insulating layer, which absorbs and guides out static electricity, reducing its entry into the internal circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the test line is configured to have a post-cutting cross-section arranged at a position as far as possible from the testing region, then the anti-electrostatic protection is improved, but the device complexity and manufacturing constraints worsen due to narrower bezels and increasing circuit complexity
Solution Approach 1:
The patent introduces an electrostatic shielding pattern as an intermediary component between the test line and the internal circuit. This shielding pattern includes a first portion positioned near the test line cross-section and a second portion extending toward the internal circuit, creating a protective barrier that blocks electrostatic discharge paths without requiring the test line to be positioned far from the testing region. The insulating layer covering the test line further mediates the isolation between test structures and internal circuits.
Solution Approach 2:
The electrostatic shielding pattern is segmented into multiple portions: a first portion positioned near the test line post-cutting cross-section and a second portion extending toward the internal circuit. This segmentation allows the shielding structure to provide comprehensive protection along the electrostatic discharge path while adapting to the constrained layout space in narrow bezel displays with complex circuits.
2Ease of operation
If the test line is exposed at a cross-section formed after the cutting process, then the testing function is maintained, but the harmful factors increase due to electrostatic charges entering through the exposed cross-section
Solution Approach 1:
The patent applies preliminary anti-action by positioning the electrostatic shielding pattern and insulating layer in advance to prevent electrostatic charges from entering the internal circuit through the exposed test line cross-section. The shielding structure is configured before the electrostatic discharge occurs, creating a protective barrier that blocks the harmful electrostatic paths while maintaining the test line's exposure for testing operations.
Solution Approach 2:
The insulating layer and electrostatic shielding pattern serve as intermediary structures that cover and protect the exposed test line cross-section. These intermediaries allow the test line to remain accessible for testing while preventing direct contact between electrostatic charges and the internal circuit, thus maintaining testing functionality while eliminating the harmful electrostatic discharge path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The electrostatic shielding pattern effectively reduces the occurrence of poor ESD and internal circuit damage by absorbing and directing static electricity away from the array substrate, enhancing the anti-electrostatic protection in display panels.
Implementation Method 1
the electrostatic shielding pattern is configured to absorb, and guide out from the array substrate, static electricity to thereby avoid the static electricity from entering an interior of the array substrate via the at least one test line
Data Source
AI summary
An array substrate is disclosed, which includes a substrate, at least one test line, an insulating layer, and an electrostatic shielding pattern. The at least one test line is disposed over the substrate. The insulating layer is disposed over the at least one test line. The electrostatic shielding pattern is disposed over, and insulated by the insulating layer from, the at least one test line in the array substrate. The electrostatic shielding pattern is configured to absorb, and guide out from the array substrate, static electricity to thereby avoid the static electricity from entering an interior of the array substrate via the at least one test line. A method for manufacturing the array substrate, and a display panel containing the array substrate are also provided in the disclosure.