Reduced Netlist for Efficient ESD Simulation of Integrated Circuits
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Solution Overview
Problem
Current ESD analysis of integrated circuits is inefficient due to the need to simulate the entire circuit design, which can lead to long simulation times, as it includes all circuitry, both relevant and irrelevant to ESD conditions, making it time-consuming and resource-intensive.
Innovation Solution
A method that selects a subset of non-ESD devices based on least resistance path and effective resistance values, generating a reduced netlist that includes only ESD devices and relevant non-ESD devices, allowing for focused ESD simulation, thereby reducing simulation time and maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire circuit design is simulated for ESD analysis, then comprehensive analysis coverage is achieved, but simulation time becomes excessively long
Solution Approach 1:
The circuit design is segmented into two categories: ESD devices (diodes, transistors, resistors connected to ESD protection circuits) and non-ESD devices. The segmentation is based on identifying devices that are directly connected to ESD protection circuits through resistance paths with resistance values below a predetermined threshold. This allows the simulation to focus only on the relevant segment (ESD devices and their connected non-ESD devices) rather than the entire circuit, thereby reducing simulation time while maintaining comprehensive analysis coverage for ESD-related components.
Solution Approach 2:
The method extracts and isolates the subset of devices relevant to ESD analysis from the complete circuit design. By identifying ESD devices and tracing their resistance paths to connected non-ESD devices, the method extracts only the necessary portion of the circuit for simulation. This extraction process removes irrelevant circuitry from the simulation scope, achieving time reduction without sacrificing the comprehensiveness of ESD analysis for the protected components.
2Productivity
If a reduced netlist is generated for ESD simulation, then simulation efficiency is improved, but analysis completeness may be compromised
Solution Approach 1:
The method applies local quality by differentiating between devices based on their relationship to ESD protection circuits. Non-ESD devices are selectively included or excluded from the reduced netlist based on their local property: whether they are connected to ESD devices through resistance paths with values below the predetermined threshold. This local quality assessment ensures that only devices with significant ESD exposure risk are included, maintaining analysis completeness for ESD-relevant components while improving simulation efficiency by excluding irrelevant ones.
Data Source
AI summary
The present embodiments relate to electrostatic discharge (ESD) simulation of integrated circuit designs. A netlist of the circuit design can be modified to include ESD protection devices and only essential non-ESD devices. The essential non-ESD devices can be determined based on whether a non-ESD device satisfies one or more of two conditions: (i) a least resistance path (LRP) value of at least one terminal of the non-ESD device from any port of the set of ports is less than a first threshold value or (ii) an effective resistance value between at least one terminal of the non-ESD device from any port of the set of ports is less than a second threshold value. The essential non-ESD devices are included in a reduced netlist in addition to the ESD protection devices. The ESD simulation is carried out on the reduced netlist, thereby reducing simulation time.