Equivalent Circuit Modeling for ESD Snapback Breakdown Simulation
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Solution Overview
Problem
Existing methods fail to accurately simulate electrostatic discharge (ESD) and electrical over stress (EOS) events during circuit design, as operations of parasitic paths are difficult to model using component models provided by foundries.
Innovation Solution
A method and apparatus using an equivalent circuit model comprising resistors, capacitors, and voltage controlled switches to simulate ESD and EOS events, allowing for the simulation of snapback breakdown and secondary breakdown of electronic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If component models provided by foundry are used for circuit simulation, then the simulation process is simple and costs are low, but the accuracy of simulating ESD and EOS events is insufficient
Solution Approach 1:
The patent introduces an equivalent circuit model as an intermediary between the simple foundry component models and the complex real-world ESD/EOS behaviors. This equivalent circuit model includes parasitic elements (inductance, resistance, capacitance) that mediate the simulation of breakdown phenomena, allowing accurate representation of snapback and secondary breakdown without requiring complex physical models
Solution Approach 2:
The patent changes the parameters of the circuit model by adding parasitic elements with specific values (e.g., inductance of 0.5-2nH, resistance of 0.1-1Ω, capacitance of 0.1-1pF) to the foundry component models. These parameter modifications enable the model to accurately simulate ESD and EOS breakdown behaviors while maintaining the simplicity of circuit simulation approaches
2Reliability
If parasitic paths are included in the circuit model to simulate ESD events, then the simulation accuracy improves, but the model complexity and difficulty of simulation increase
Solution Approach 1:
The patent segments the ESD simulation model into distinct functional components: parasitic inductance elements, parasitic resistance elements, parasitic capacitance elements, and voltage-controlled switches for breakdown simulation. Each segment handles a specific aspect of ESD behavior, making the overall complex model manageable and simulatable using standard circuit simulation tools
Solution Approach 2:
The patent employs dynamic voltage-controlled switches that activate based on voltage thresholds to simulate the dynamic breakdown behavior of electronic components during ESD events. The switches transition between on and off states based on simulated voltage levels, enabling the model to capture the transient nature of ESD breakdown without requiring complex time-dependent models
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective simulation of ESD and EOS events during circuit design, facilitating primary evaluation of circuit endurance without significant additional costs or side effects.
Implementation Method 1
a first voltage controlled switch of the equivalent circuit model to increase a voltage level of a second node of the equivalent circuit model; and in response to the voltage level of the second node reaching a second threshold, turning on a second voltage controlled switch of the equivalent circuit model
Data Source
AI summary
A method and apparatus for simulating breakdown of an electronic component are provided. The method includes: when a terminal of an equivalent circuit model receives test charges, pulling up a voltage level of a first node of the equivalent circuit model; when the voltage level of the first node reaches a first threshold, turning on a first voltage controlled switch to pull up a voltage level of a second node of the equivalent circuit model; when the voltage level of the second mode reaches a second threshold, turning on a second voltage controlled switch to pull down a voltage level of the terminal to a holding voltage level to simulate snapback breakdown of the electronic component; and turning on a third voltage controlled switch to pull down the voltage level of the second node to turn off the second voltage controlled switch, thereby simulating second breakdown of the electronic component.