ESD Protection in Stacked Chips via Localized RC Clamp Design
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Solution Overview
Problem
Existing multi-chip stacked devices face challenges in effectively managing electrostatic discharge (ESD) protection, particularly in decoupling discharge paths to prevent ESD current crowding and ensuring adequate protection across different ESD event types like Human Body Model (HBM) and Charged Device Model (CDM) without increasing manufacturing costs.
Innovation Solution
The implementation of a chip stack design where a base chip has a larger RC-time constant RC clamp compared to other chips, with RC clamps on other chips having smaller footprints and thus smaller RC-time constants, allowing for effective ESD protection by containing HBM discharge within the base chip and using smaller RC clamps for CDM events, which are less costly to manufacture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform large RC-time constant clamp is used in all chips of the stack, then HBM ESD protection is adequate, but manufacturing cost increases and chip area is wasted
Solution Approach 1:
The patent applies local quality by differentiating the RC-time constant of ESD clamps based on their location in the chip stack. The base chip (first chip) uses a larger RC-time constant clamp to handle HBM events from external connectors, while upper chips (second and subsequent chips) use smaller RC-time constant clamps sufficient for CDM events only. This localized differentiation optimizes both protection effectiveness and manufacturing cost by avoiding over-protection in chips that don't require it.
2Reliability
If ESD protection is provided in all chips with sufficient clamp size, then ESD current crowding is avoided, but device complexity and cost increase
Solution Approach 1:
The patent segments the ESD protection strategy into two distinct levels: the base chip receives full HBM-level protection with a larger RC-time constant clamp, while upper chips receive CDM-level protection with smaller RC-time constant clamps. This segmentation allows each chip to have appropriately sized protection without requiring all chips to have the largest possible clamps, thereby reducing overall device complexity and cost while maintaining adequate protection at each level.
3Ease of manufacture
If smaller RC clamps are used in upper chips, then manufacturing cost is reduced, but protection against HBM events may be insufficient
Solution Approach 1:
The base chip acts as an intermediary that absorbs and handles HBM-level ESD events before they can propagate to upper chips. The larger RC-time constant clamp in the base chip provides the necessary protection for HBM events, allowing upper chips to use smaller clamps designed only for CDM events. This intermediary role of the base chip enables cost reduction in upper chips without compromising overall system protection against HBM events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively decouples ESD discharge paths, ensuring robust protection against both HBM and CDM events while reducing manufacturing costs by allowing smaller, less expensive components in non-base chips.
Implementation Method 1
electrostatic discharge (ESD) protection in stacked chips
Implementation Method 2
A RC-time constant of a resistor-capacitor (RC) clamp on a base chip in a chip stack can be greater than a RC-time constant of a RC clamp on other chip(s) of the chip stack
Data Source
AI summary
Examples described herein generally relate to devices that include electrostatic discharge (ESD) protection in a chip stack. In an example, a device includes a chip stack including first and second chips, ground and power supply voltage nodes, and first and second resistor-capacitor (RC) clamps. The second chip is disposed on and attached to the first chip. The ground and power supply voltage nodes are connected between and extend in the first and second chips, and are connected to the ground and power supply voltage exterior connector pads, respectively, of the first chip. The first and second RC clamps are disposed in the first and second chips, respectively. The first and second RC clamps are connected to and between the ground node and the power supply voltage node. An RC-time constant of the second RC clamp is less than an RC-time constant of the first RC clamp.