ESD Suppressor With Insulating Frame And Cavity
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Solution Overview
Problem
Existing ESD suppressors face challenges in achieving higher breakdown voltage, faster response rates, and reduced circuit board area, especially in wearable devices and touch panels where static electric signals and noise are more prevalent, making it difficult to protect integrated circuits from abnormal signals.
Innovation Solution
The ESD suppressor design involves two printed circuit boards positioned on opposite sides of an insulating frame, with interior electrodes exposed to a cavity, allowing adjustment of the breakdown voltage by varying the thickness of the insulating frame and spatial configuration of the electrodes, which are electrically insulated to prevent discharge to the exterior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the insulating frame is increased to increase the breakdown voltage, then the breakdown voltage increases, but the device size increases
Solution Approach 1:
The patent transitions from a planar electrode arrangement to a three-dimensional configuration by positioning electrodes on opposite surfaces of the insulating frame. This spatial arrangement increases the breakdown voltage through the insulating frame thickness without proportionally increasing the device footprint, effectively resolving the contradiction between reliability and area.
2Area of stationary object
If the interior electrodes are positioned closer together to reduce device area, then the device area is reduced, but the breakdown voltage decreases
Solution Approach 1:
By moving the electrode separation distance from a planar dimension to a three-dimensional configuration across the insulating frame thickness, the patent achieves compact device area while maintaining high breakdown voltage through the vertical insulation barrier.
Solution Approach 2:
The insulating frame acts as an intermediary structure that separates the interior electrodes on opposite surfaces. This mediator provides the necessary electrical insulation to maintain high breakdown voltage while allowing the electrodes to be positioned in a compact three-dimensional arrangement.
3Reliability
If conventional ESD suppressor structures are used to protect integrated circuits, then the protection function is provided, but the response rate is slow and the circuit board area is large
Solution Approach 1:
The patent optimizes the geometric parameters of the capacitor structure, including the insulating frame thickness and electrode configuration, to achieve faster response rate. By changing the physical dimensions and spatial arrangement, the ESD suppressor responds more quickly to transient signals while maintaining protection function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively increases the breakdown voltage and reduces parasitic capacitance, allowing for better protection of integrated circuits from high-voltage signals while minimizing the negative impact on the printed circuit boards and electrodes, and can be manufactured using a simple and cost-effective process without high-temperature requirements.
Implementation Method 1
an insulating frame positioned between the two printed circuit board... different interior electrodes are separated away each other... electrically insulated to prevent discharge to the exterior
Implementation Method 2
the capacitance inside the ESD suppressor 101 prevent the signal from passing through the ESD suppressor 101... when the voltage of the signal from the circuit 103 does not exceed the breakdown voltage of the ESD suppressor 101
Implementation Method 3
when the voltage of the signal from the circuit 103 does exceed the breakdown voltage of the ESD suppressor 101, the capacitance inside the ESD suppressor 101 can not prevent the signal from passing through the ESD suppressor 101 into the potential ground 103
Data Source
Figure 1A~1B
Figure 2A
Figure 2B
AI summary
ESD suppressor and manufacturing method thereof. The ESD suppressor include at least two printed circuit boards, one insulating frame, two terminal electrodes and two or more interior electrodes. The insulating frame is positioned between the two printed circuit boards, so as to form a main structure with a cavity. For each printed circuit board, at least one interior electrode is positioned on the surface facing the cavity and separated from other interior electrode(s). Two terminal electrodes are positioned on two different surfaces of the main structure and electrically connected to different interior electrodes respectively. Optionally, the insulating frame is a hallowed out printed circuit board or a frame formed by printing insulating material. In the manufacturing method, the thickness of the insulating frame is adjusted to adjust the relative distance between different printed circuit boards, so as to further adjust the breakdown voltage of the ESD suppressor