Automated ESD Test Bench Generation from IC Netlists
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Solution Overview
Problem
Conventional methods for testing electrostatic discharge (ESD) protection circuits in integrated circuits (ICs) are cumbersome, time-consuming, and prone to errors due to the manual setup of test benches, which can lead to inaccurate results.
Innovation Solution
An automated system that generates a test bench circuit based on the IC design's netlist, using a resistance inductance capacitance (RLC) circuit to simulate ESD events according to human body model (HBM) or charged device model (CDM) stimuli, allowing for parameter calculation and modification, and providing accurate ESD stimulus to the IC's pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual test bench setup is used for ESD testing, then circuit designers can test ESD protection circuits, but the process becomes cumbersome, time-consuming, and prone to errors
Solution Approach 1:
The system enables self-service automation where the computer automatically generates test benches by extracting parameters from the netlist file and configuring RLC circuits without requiring manual intervention from circuit designers. This eliminates the cumbersome manual setup process while maintaining testing accuracy through automated parameter extraction and test bench configuration.
Solution Approach 2:
The system performs preliminary actions by automatically extracting circuit parameters from the netlist file before generating the test bench. This preliminary parameter extraction and analysis enables the subsequent automatic generation of accurate test benches, eliminating the need for time-consuming manual setup while ensuring testing reliability through pre-configured accurate parameters.
2Reliability
If manual test bench setup is used for ESD testing, then testing can be performed, but the process is prone to errors leading to invalid test results
Solution Approach 1:
The system performs self-service by automatically extracting parameters from the netlist file and configuring the test bench without manual intervention. This automation eliminates human errors in parameter extraction and test bench configuration, ensuring valid test results while reducing the perceived complexity for users through automated processes.
Solution Approach 2:
The system replaces the manual mechanical process of test bench setup with an automated computer-based system. The computer automatically extracts parameters from the netlist, calculates RLC values, and generates test benches, substituting the manual mechanical configuration process with an automated electronic system that eliminates errors and reduces complexity.
3Productivity
If automated test bench generation is implemented, then testing efficiency is improved, but the system requires parameter extraction and calculation capabilities
Solution Approach 1:
The system performs preliminary parameter extraction from the netlist file before test bench generation. This preliminary action of extracting and storing circuit parameters enables rapid automated test bench generation without requiring complex real-time calculations during the generation process, thus improving productivity while managing system complexity through pre-processing.
Solution Approach 2:
The system uses the netlist file as an intermediary that contains all necessary circuit parameters. By extracting parameters from this intermediary representation of the circuit, the system enables automated test bench generation without requiring direct complex interactions with the actual circuit, thus improving productivity while keeping the system manageable through standardized parameter extraction.
Data Source
AI summary
Disclosed herein are embodiments of systems, methods, and products to automatically and intelligently generate a test bench to test an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) design. A computer may receive netlist of the IC design forming a device under test (DUT). From the DUT, the computer may extract and/or calculate one or more parameters. Based on the one or more parameters, the computer may generate a test bench comprising a resistance inductance capacitance (RLC) circuit to provide ESD stimulus to the DUT. The ESD stimulus and therefore the test bench may be based on a human body model (HBD) or a charged device model (CDM). In case of the CDM, the computer may allow a circuit designer to select or deselect package parameters for testing the ESD protection circuit.


