ESD Transistor Array with Non-Uniform Dissipation Contacts

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Solution Overview

Problem

Existing ESD transistor array apparatuses suffer from uneven heat dissipation, leading to poorer performance as heat generated in the middle region is not effectively dissipated, causing devices on the edge to remain unturned and potentially leading to second breakdown.

Innovation Solution

The ESD transistor array apparatus incorporates a dissipation layer contact member on each gate, with decreasing density towards the substrate contact region, ensuring higher density in the middle region for enhanced heat dissipation and maintaining even operation across the array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If heat dissipation is improved in the middle region of the array, then ESD performance is improved, but device complexity increases due to non-uniform dissipation layer contact member density

Engineering Contradiction:
ImproveESD performanceVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dissipation layer contact members are configured with non-uniform density where the first dissipation layer contact member is disposed on the first gate and the second dissipation layer contact member is disposed on the second gate, creating different contact densities in different regions of the array. This local differentiation optimizes heat dissipation in the middle region while maintaining uniformity in edge regions, improving ESD performance without excessive complexity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The array is segmented into different regions (edge regions with first gates and middle region with second gates) with different dissipation layer contact member configurations. This segmentation allows targeted heat dissipation optimization in the middle region while maintaining simpler structures in edge regions where less heat dissipation is needed

Inventive Principle:
Principle #1Segmentation

2Reliability

If uniform heat dissipation is achieved across the array, then all devices can operate evenly, but manufacturing precision requirements increase

Engineering Contradiction:
Improveuniform operationVSAvoidmanufacturing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

Rather than implementing uniform high-density contact members across the entire array, the invention applies different contact member configurations to different regions: first dissipation layer contact members for edge region gates and second dissipation layer contact members for middle region gates. This localized approach achieves uniform heat dissipation across the array while reducing manufacturing precision requirements compared to a fully uniform high-density design

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration achieves uniform heat dissipation, preventing premature voltage increase in the middle region and ensuring all devices in the array can operate evenly, thereby improving overall performance and preventing damage from second breakdown.

Implementation Method 1

density of the dissipation layer contact member decreases with a decrease in a distance from the gate on which the dissipation layer contact member is located to the first contact region part

Methodology Applied
Scientific EffectHeat conduction: Conduction (thermal)

Implementation Method 2

When ESD occurs, an avalanche occurs in a depletion region of the drain and the substrate, accompanied by generation of an electron hole pair

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS10396066B2Electro-static discharge transistor array apparatus
Publication Date: 2019.08.27 SEMICON MFG INT (SHANGHAI) CORP
  • US10396066B2 patent drawing
  • US10396066B2 patent drawing
  • US10396066B2 patent drawing

AI summary

The present application discloses an electro-static discharge (ESD) transistor array apparatus, and relates to the field of semiconductor technologies. The ESD transistor array apparatus may include: a semiconductor substrate, the semiconductor substrate including a semiconductor layer, a doped region on the semiconductor layer, and a substrate contact region, where the doped region and the substrate contact region are isolated, and where the substrate contact region includes at least a first contact region part separately disposed on two sides of the doped region; multiple gates arranged in parallel on the doped region, where a direction of extension of the multiple gates is in parallel with a direction of extension of the first contact region part; and a dissipation layer contact member disposed on each gate along the direction of extension of the gate, where density of the dissipation layer contact member decreases with a decrease in a distance from the gate on which the dissipation layer contact member is located to the first contact region part on a corresponding side. By means of the present disclosure, uniform heat dissipation of an ESD transistor array apparatus can be achieved.