ESD Transistor With Nested Source Wells
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Solution Overview
Problem
Integrated circuits face challenges in protecting against electrostatic discharge (ESD) due to the size limitations of high voltage ESD transistors, which require larger footprints for higher trigger and holding voltages, and struggle to handle larger current loads effectively.
Innovation Solution
The integration of a deep well with a drain well and multiple source wells of varying conductivity impurity concentrations, where the second source well has a higher concentration than the first, allowing for increased trigger and holding voltages without increasing the transistor footprint, and enabling higher current capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage ESD transistor designs are used to achieve higher trigger and holding voltages, then the protection capability against ESD events is improved, but the transistor footprint increases
Solution Approach 1:
The patent applies local quality by creating multiple source wells with different impurity concentrations in specific locations within the transistor structure. The first source well has a lower concentration and the second source well has a higher concentration, allowing different regions to contribute differently to the trigger and holding voltages, thereby achieving high voltage protection without proportionally increasing the overall footprint.
Solution Approach 2:
The patent implements nesting by placing the second source well within or adjacent to the first source well region. This nested arrangement allows the higher concentration second source well to contribute to the holding voltage while the lower concentration first source well contributes to the trigger voltage, achieving high protection capability within a compact nested structure rather than requiring separate large regions.
2Reliability
If traditional ESD transistor designs are used, then the manufacturing process is simple, but the current carrying capacity is limited
Solution Approach 1:
The patent uses local quality by doping different regions (source wells) with different impurity concentrations. The first source well with lower concentration and the second source well with higher concentration create localized variations in electrical properties, enabling the transistor to handle larger current loads while maintaining a manageable structural complexity through targeted regional modifications.
Data Source
AI summary
Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a deep well with a drain well overlying the deep well. A first source well also overlies the deep well, where the first source well includes a first source well concentration of conductivity determining impurities. A second source well overlies the first source well, where the second source well includes a second concentration of conductivity determining impurities that is higher than the first source well concentration. A drain overlies the drain well and a source overlies the second source well. A channel is defined between the source and the drain and a gate overlies the channel.