ESD Protection Transistor with Non-Uniform Pathway Resistance
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Solution Overview
Problem
Semiconductor devices face challenges in effectively managing electrostatic discharge (ESD) protection, particularly in ensuring uniform current distribution across ESD protection transistors to prevent overloading and improve ESD breakdown voltage.
Innovation Solution
The semiconductor device incorporates a configuration with multiple GGNMOS transistors connected in parallel, where the source and drain wirings are alternately arranged to distribute discharge current evenly, with varying resistance values in the current pathways to ensure uniform current flow through each transistor, thereby reducing the risk of transistor breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple ESD protection transistors are connected in parallel to handle high-voltage pulses, then the ESD protection capability is improved, but the current distribution becomes uneven causing some transistors to be overloaded
Solution Approach 1:
The patent applies local quality by making the resistance values of current pathways non-uniform. Specifically, different resistance values are assigned to different current pathways based on their position and characteristics, ensuring that current distributes evenly across all parallel transistors. This resolves the contradiction by locally adjusting resistance parameters to achieve global current uniformity while maintaining high ESD protection capability.
Solution Approach 2:
The patent changes the resistance parameter of current pathways to control current distribution. By adjusting resistance values in different pathways, the patent ensures uniform current flow through parallel transistors, preventing overload and improving reliability without sacrificing protection capability.
2Reliability
If more transistors are used to improve ESD breakdown voltage, then the ESD protection performance is enhanced, but the chip area increases
Solution Approach 1:
The patent merges multiple ESD protection transistors into a single integrated structure with shared current pathways. By combining transistors and their associated resistance elements into a unified design, the patent achieves high ESD breakdown voltage while minimizing the total chip area required compared to discrete transistor arrangements.
Solution Approach 2:
The patent creates a multi-functional ESD protection structure where a single integrated circuit block performs both current distribution control and voltage protection functions. This universal design eliminates the need for separate components, reducing overall chip area while maintaining enhanced ESD breakdown voltage capability.
Data Source
AI summary
According to one embodiment, an electrostatic discharge semiconductor device includes one or more wiring layers first disposed over a substrate, including: a wiring electrically connected at a first connecting point of a pad, a second wiring electrically connected at a second connecting point of a ground wiring, and a third wiring electrically connected at a third connecting point of the ground wiring; a first transistor formed in the substrate comprising a first diffusion region electrically connected to the first wiring, a second diffusion region electrically connected to the second wiring, and a gate electrically connected to the ground wiring; and a second transistor formed in the substrate comprising the first diffusion region electrically connected to the first wiring, a third diffusion region electrically connected to the third wiring, and a gate electrically connected to the ground wiring, wherein, a first resistance value of a first current pathway leading from the first connecting point to the second connecting point via the first transistor is different from a second resistance value of a second current pathway leading from the first connecting point to the third connecting point via the second transistor.