ESD Protection Transistor String with Reduced Triggering Voltage
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Solution Overview
Problem
Existing ESD protection apparatuses with thin gate oxides suffer from high leakage currents during normal operation and are difficult to trigger, leading to reduced protection effectiveness, while those with thick gate oxides are hard to activate, often resulting in damage before protection is initiated due to the high triggering voltage requirements of conventional SCRs.
Innovation Solution
The use of multiple series-connected transistors with specific terminal and bulk connections to reduce the triggering voltage of parasitic silicon controlled rectifiers (SCRs), allowing for immediate conduction of ESD currents and minimizing damage to gate oxides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection elements have thin gate oxides, then ESD protection capability is improved, but leakage current increases during normal operation
Solution Approach 1:
The patent divides the ESD protection function into multiple transistor stages (first transistor string and second transistor string) connected in series. This segmentation allows the system to achieve low triggering voltage for ESD protection while maintaining higher threshold voltages during normal operation, thus reducing leakage current. Each transistor string contains multiple transistors with specific gate oxide thicknesses that work together to provide both protection capability and low leakage.
2Reliability
If conventional SCR is used for ESD protection, then ESD protection function is provided, but triggering voltage is too high causing damage before protection activates
Solution Approach 1:
The patent changes the triggering voltage parameter by using multiple transistors with carefully selected threshold voltages in series configuration. The combined triggering voltage of the transistor strings is lower than that of conventional SCR, enabling the protection mechanism to activate before ESD damage occurs. The parameter adjustment is achieved through selecting transistors with appropriate threshold voltages and configuring their connection topology.
3Object-generated harmful factors
If ESD protection apparatus is constructed with thick gate oxides, then leakage current is reduced, but triggering becomes difficult and protection effect is reduced
Solution Approach 1:
The patent applies local quality by using transistors with different gate oxide thicknesses in different positions within the transistor strings. Some transistors have thinner gate oxides to facilitate triggering, while others have thicker gate oxides to reduce leakage. This spatial variation in gate oxide quality allows the system to simultaneously achieve low leakage current during normal operation and easy triggering during ESD events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the triggering voltage of SCRs, enabling immediate discharge of ESD currents and enhancing the protection of thin gate oxides by ensuring quicker conduction and reduced leakage currents during normal operation.
Implementation Method 1
utilizes a parasitic silicon controlled rectifier (SCR) for electrostatic protection
Implementation Method 2
electrostatic discharge (ESD) event
Data Source
AI summary
An electrostatic discharge (ESD) protection apparatus includes at least one first transistor and at least one second transistor. The first transistor includes a control terminal, a first terminal, a second terminal, and a bulk. The control terminal and the second terminal of the first transistor are coupled to each other. The first terminal of the first transistor is coupled to one of a pad and a power rail line. Likewise, the second transistor also includes a control terminal, a first terminal, and a second terminal. The first terminal of the second transistor is coupled to the bulk of the first transistor, the bulk of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the other of the pad and the power rail line.