ESD Protection Transistor Thyristor Integration

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Solution Overview

Problem

Integrated circuits are vulnerable to damage from electrostatic discharge (ESD) due to their small size and increased susceptibility to voltage breakdown, with existing ESD protection devices often failing to effectively shield against rapid ESD pulses, particularly those with short rise-times, which can lead to voltage overshoots and damage to gate oxides.

Innovation Solution

A semiconductor device comprising a transistor and a thyristor combination, where the transistor triggers rapidly to provide an initial discharge path for ESD pulses and the thyristor activates later to offer a lower resistance path for longer pulse durations, effectively protecting sensitive circuitry from both initial and subsequent ESD events.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single ESD protection device is used, then the device structure is simple, but it cannot effectively protect against rapid ESD pulses with short rise-times due to voltage overshoots

Engineering Contradiction:
ImproveESD protection device structureVSAvoidprotection effectiveness against rapid ESD pulses
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The ESD protection device is segmented into two distinct functional components: a first ESD protection device (e.g., diode or transistor) for initial pulse detection and a second ESD protection device (e.g., thyristor or SCR) for sustained current diversion. This segmentation allows each component to be optimized for its specific function, resolving the contradiction by achieving both structural simplicity and protection effectiveness through functional division.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first ESD protection device performs preliminary action by detecting the ESD pulse and triggering the second ESD protection device before the pulse can cause damage. This preliminary detection and triggering mechanism ensures that the main protection device is activated in time, preventing voltage overshoots from damaging sensitive circuitry while maintaining overall system simplicity.

Inventive Principle:
Principle #10Preliminary action

2Speed

If the ESD protection device is rapidly triggered, then protection response time is improved, but voltage overshoots may still destroy gate oxides connected to the protected node

Engineering Contradiction:
ImproveESD device trigger speedVSAvoidvoltage overshoot damage to gate oxides
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The first ESD protection device acts as an intermediary between the ESD pulse and the second ESD protection device. It detects the pulse and initiates triggering of the second device, serving as a mediator that enables rapid response while preventing direct voltage overshoot damage to sensitive nodes. This intermediary mechanism resolves the contradiction by decoupling the trigger initiation from the main current diversion function.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Volume of moving object

If transistor physical size is reduced to increase integration density, then device miniaturization is achieved, but breakdown voltage decreases and susceptibility to ESD damage increases

Engineering Contradiction:
Improvetransistor physical sizeVSAvoidESD susceptibility
Core Design Contradiction:
Volume of moving objectVSObject-affected harmful factors

Solution Approach 1:

The ESD protection function is merged with the existing transistor structure by forming the protection device using the transistor's source, drain, and substrate regions. This merging allows the protection function to be integrated without requiring additional discrete components, achieving both miniaturization and enhanced ESD susceptibility protection through structural integration.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The transistor's own substrate and doped regions are utilized to form the ESD protection device, allowing the transistor to protect itself from ESD damage. This self-service approach eliminates the need for external protection components, enabling device miniaturization while maintaining robust ESD protection capabilities through intelligent use of existing structures.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The transistor-thyristor combination effectively shields integrated circuits from ESD damage by providing a rapid discharge path for initial ESD pulses and a lower resistance path for extended pulses, preventing transistor breakdown and ensuring reliable operation.

Implementation Method 1

electro static discharge (ESD) is the transfer of an electrostatic charge between bodies at different electrostatic potentials or voltages

Methodology Applied
Scientific EffectElectrostatic discharge: Electrostatic Discharge

Implementation Method 2

the extremely high voltage of the ESD pulse can break down the transistor

Methodology Applied
Scientific EffectVoltage breakdown: Avalanche Breakdown

Data Source

PatentUS8198651B2Electro static discharge protection device
Publication Date: 2012.06.12 INFINEON TECHNOLOGIES AG
  • US8198651B2 patent drawing
  • US8198651B2 patent drawing
  • US8198651B2 patent drawing

AI summary

A semiconductor device for protecting against an electro static discharge is disclosed. In one embodiment, the semiconductor device includes a first low doped region disposed in a substrate, a first heavily doped region disposed within the first low doped region, the first heavily doped region comprising a first conductivity type, and the first low doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first heavily doped region being coupled to a node to be protected. The semiconductor device further includes a second heavily doped region coupled to a first power supply potential node, the second heavily doped region being separated from the first heavily doped region by a portion of the first low doped region, and a second low doped region disposed adjacent the first low doped region, the second low doped region comprising the first conductivity type. A third heavily doped region is disposed in the second low doped region, the third heavily doped region comprising the second conductivity type and being coupled to a second power supply potential node.