ESD Transistor with U-Shaped Current Path for High Voltage Protection
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Solution Overview
Problem
Existing ESD protection circuits face difficulties in shunting high-level ESD currents while maintaining low clamping voltages, particularly in high-voltage applications, leading to increased turn-on voltage and snapback effects that can damage core circuits.
Innovation Solution
The ESD transistor design features a collector region, sink region, and buried layer forming a U-shaped current path, along with a charge pump circuit and diodes, to create an extended current path and reduce clamping voltage, allowing for efficient shunting of high-level ESD currents and rapid turn-on operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the doping concentration in the source and drain is reduced to maintain high breakdown voltage, then the breakdown voltage is improved, but the ability to shunt high-level ESD currents deteriorates
Solution Approach 1:
The source/drain structure is segmented into multiple regions with different doping concentrations. The collector region has low doping concentration for high breakdown voltage, while the sink region has high doping concentration for effective ESD current shunting. This segmentation allows each region to optimize its function independently.
Solution Approach 2:
Different regions of the transistor are assigned different local properties: the collector region maintains low doping concentration for high voltage operation, while the sink region introduces high doping concentration specifically for ESD protection. This local quality differentiation resolves the contradiction between breakdown voltage and ESD current handling.
2Strength
If high voltage operation is implemented, then the voltage handling capability is improved, but the turn-on voltage increases and snapback effects occur
Solution Approach 1:
The sink region acts as an intermediary between the collector and substrate, providing a controlled path for ESD current. This intermediary structure prevents direct high-current flow through the collector-base junction, thereby reducing snapback effects while maintaining high voltage handling capability.
Solution Approach 2:
The invention introduces a vertical dimension with the sink region extending below the collector region. This three-dimensional structure creates an extended current path that reduces the lateral electric field strength, thereby mitigating snapback effects while preserving high voltage operation.
3Reliability
If the current path is extended to reduce clamping voltage, then the ESD protection performance is improved, but the device area increases
Solution Approach 1:
The current path is extended in the vertical dimension by introducing the sink region below the collector region, rather than extending it laterally. This vertical extension achieves longer current path length for reduced clamping voltage without proportionally increasing the device footprint area.
Solution Approach 2:
The sink region is nested within the device structure below the collector region, utilizing the vertical space efficiently. This nesting approach extends the current path length without requiring additional lateral area, thereby improving ESD protection performance within a compact footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces clamping voltage, enhances the ability to handle high stress currents and voltages, and prevents thermal breakdown, enabling stable operation of high-voltage core circuits with improved ESD protection and reduced chip size.
Implementation Method 1
a sink region disposed vertically below the collector region; and a buried layer protruding horizontally further than the sink region under the sink region
Data Source
AI summary
An ESD transistor and an ESD protection circuit thereof are provided. An ESD transistor includes a collector region disposed on a surface of a substrate, a sink region disposed vertically below the collector region, and a buried layer protruding horizontally further than the sink region under the sink region.