ESD Trigger Circuit for Semiconductor Integrated Circuits
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Solution Overview
Problem
Semiconductor integrated circuits face challenges in properly triggering thyristors as ESD protection devices, especially at low voltages, leading to potential breakdown of NMOS transistors due to excessive current flow before the thyristor operates, and also struggle with high output capacitance that hampers high-speed signal output.
Innovation Solution
Incorporating a trigger MOS transistor that detects voltage generated by a resistance element connected between the protection target device and ground, allowing the thyristor to be triggered reliably before the NMOS transistor is subjected to breakdown, while also isolating the thyristor's gates from the output pad to reduce output capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a resistance element is added to detect surge current, then triggering reliability is improved, but output capacitance increases
Solution Approach 1:
The patent applies segmentation by separating the surge detection function from the output signal path. Instead of placing a resistance element directly in the output path (which would increase output capacitance), the detection is performed through a dedicated trigger device connected to the protection target device. This segmentation allows the resistance element to be isolated from the high-speed output path, maintaining signal integrity while enabling reliable surge detection and triggering.
2Device complexity
If the gate of NMOS transistor is in floating state, then circuit complexity is reduced, but current control capability deteriorates
Solution Approach 1:
The patent applies the intermediary principle by introducing a trigger device as a mediator between the protection target device and the thyristor. The trigger device includes a transistor whose gate is connected to the protection target device, serving as an intermediate control element. This intermediary structure provides a defined voltage reference and control path without significantly increasing overall circuit complexity, while ensuring proper current control capability during ESD events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures reliable triggering of the ESD protection device while minimizing output capacitance, allowing for efficient high-speed signal output without risking transistor breakdown.
Implementation Method 1
a first resistance element connected between the first protection target device and the first interconnection. The first trigger MOS transistor configured to detect a voltage generated in the first resistance element
Implementation Method 2
an ESD protection device connected with the output signal line and having a function to discharge surge applied to the output pad
Data Source
AI summary
A semiconductor integrated circuit includes: an output pad from which an output signal is outputted; an output signal line connected with the output pad; a first pad configured to function as a ground terminal or a power supply terminal; a first wiring connected with the first pad; an output driver connected with the output pad and configured to generate the output signal; an ESD protection device connected with the output signal line and having a function to discharge surge applied to the output pad; and a first trigger MOS transistor used as a trigger device. The output driver includes: a first protection target device connected between the output signal line and the first interconnection; and a first resistance element connected between the first protection target device and the first interconnection. The first trigger MOS transistor configured to detect a voltage generated in the first resistance element by a gate of the first trigger MOS transistor and to allow the ESD protection device operate in response to the detected voltage.