ESD Protection Structure With Auxiliary Trigger Path for Low Voltage
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Solution Overview
Problem
Existing ESD protection structures in semiconductors have high trigger voltages, making them ineffective at timely discharge of static electricity at low electro-static voltages.
Innovation Solution
The proposed ESD protection structure includes a semiconductor substrate with specific doped regions and wells, forming a PNP-type triode and NPN-type triode configuration with an auxiliary trigger current path, allowing for low trigger voltage and fast discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If commonly used ESD protection structures (MOS transistors, diodes, thyristors) are employed, then the ESD protection function is provided, but the trigger voltage is high and cannot be triggered timely at low electro-static voltage
Solution Approach 1:
The ESD protection structure is divided into multiple doped regions (first P-type doped portion, first N-type doped portion, second P-type doped portion, second N-type doped portion, third P-type doped portion, third N-type doped portion) and wells (first P-type well, first N-type well, third doped well) that work together in sequence. This segmentation allows the structure to be triggered at low voltage while maintaining effective ESD protection function.
Solution Approach 2:
The patent changes the doping parameters and well structure parameters to achieve low trigger voltage. By optimizing the doping concentrations and well depths, the ESD protection structure can be triggered at low electro-static voltage levels while maintaining its protection capability.
2Object-affected harmful factors
If the ESD protection structure is designed to trigger at low voltage, then the trigger voltage is reduced, but the discharge speed may be compromised
Solution Approach 1:
The doped regions and wells are pre-configured in specific positions and concentrations during manufacturing. This preliminary arrangement ensures that when low voltage is applied, the charge carriers are already in optimal positions to enable rapid discharge, achieving both low trigger voltage and fast discharge speed.
Solution Approach 2:
The various doped portions and wells act as intermediaries that facilitate the discharge process. The first P-type doped portion, first N-type doped portion, and associated wells serve as intermediate structures that enable efficient charge transfer and rapid discharge while being triggered at low voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ESD protection structure achieves a low trigger voltage and fast starting speed, effectively discharging static electricity and protecting core circuits from damage.
Implementation Method 1
The ESD protection circuit is used to discharge static electricity in the chip, to avoid damage to a core circuit in the chip under action of the static electricity
Implementation Method 2
the second N-type doped portion, the second P-type doped portion and the third N-type doped portion are electrically connected; and the first N-type doped portion is electrically connected to the third P-type doped portion
Data Source
AI summary
The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.