ESD Protection Circuit with Triggered Parasitic Transistors
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Solution Overview
Problem
Conventional ESD protection circuits for ICs have low electrostatic discharge efficiency due to a single passive discharge path, which is insufficient for deep sub-micron CMOS ICs prone to electrostatic damage.
Innovation Solution
The proposed ESD protection structure incorporates a PMOS transistor, NMOS transistor, and multiple parasitic transistors with an external trigger-voltage adjustment circuit to create multiple active discharge paths, enhancing discharge efficiency and control over parasitic transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional NMOS transistor with grounded gate is used for ESD protection, then the circuit has good compatibility with CMOS technology, but the electrostatic discharge efficiency is low due to a single passive discharge path
Solution Approach 1:
The ESD protection circuit is divided into multiple functional modules: a PMOS transistor for power supply discharge path, an NMOS transistor for ground discharge path, and trigger circuits for active control. Each module handles specific discharge functions, transforming the single passive path into multiple active paths while maintaining CMOS process compatibility
Solution Approach 2:
The invention transitions from a static passive discharge path to dynamic active discharge paths by introducing trigger circuits that activate parasitic transistors. The external trigger-voltage adjustment circuit dynamically controls the discharge paths based on ESD event detection, enabling timely and efficient electrostatic charge dissipation
2Productivity
If multiple parasitic transistors are introduced to increase discharge paths, then the electrostatic discharge efficiency improves, but the device complexity increases
Solution Approach 1:
The circuit utilizes naturally occurring parasitic transistors inherent in the CMOS fabrication process rather than adding completely separate components. These parasitic structures are already present due to the well and region configurations, and the invention simply activates them through trigger circuits, avoiding significant additional complexity
Solution Approach 2:
The parasitic transistors serve dual purposes: they are byproducts of the standard CMOS device structure and simultaneously function as active ESD discharge elements. The external trigger-voltage adjustment circuit provides universal control over multiple discharge paths, managing both PMOS and NMOS transistor activation through a single control mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the number of electrostatic discharge paths and improves discharge efficiency, allowing for timely and effective discharge of accumulated electrostatic charge, while maintaining compatibility with CMOS technology and reducing manufacturing costs.
Implementation Method 1
the external trigger-voltage adjustment circuit is configured to pull down an electric potential of the first doped base region when the power supply terminal generates an instantaneous electric potential difference
Implementation Method 2
When the electric potential difference becomes greater than a threshold voltage of the parasitic NPN transistor 17, the parasitic NPN transistor 17 is in a conductive state. In this case, current flows from the drain region 102 to the source region 104 to discharge the electrostatic charge accumulated on the I/O interface terminal 15
Data Source
AI summary
An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. A second doped base region located in the fourth region of the first P-type well region is P-type doped and connected to the external trigger-voltage adjustment circuit. The external trigger-voltage adjustment circuit can be configured to pull up an electric potential of the second doped base region when the power supply terminal generates an instantaneous electric potential difference.