Semiconductor ESD Protection Via Placement
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Solution Overview
Problem
Existing semiconductor devices face challenges in defining the layout of multi-finger NMOS transistors for effective ESD protection due to the difficulty in quantifying the dependency of ESD tolerance on layout dimensions, especially when dealing with large and instantaneous surge currents.
Innovation Solution
A semiconductor device design featuring an NMOS transistor under a pad with alternately formed source and drain diffusion regions, a gate electrode, and a specific arrangement of metal films and vias that ensures uniform current flow and increased ESD tolerance without defining the dimensions of the layout, including a lower metal film, an intermediate metal film with a rectangular ring shape, and a first via directly above the drain for connecting the pad to the NMOS transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the layout dimensions of the multi-finger NMOS transistor are not defined, then the ESD tolerance can be increased without quantification difficulties, but the uniform operation of channels cannot be ensured
Solution Approach 1:
The patent changes the approach from defining layout dimensions to controlling the electrical connection structure. Specifically, it positions the first via directly above the drain region and uses an intermediate metal film with rectangular ring shape to create symmetrical electrical pathways, thereby ensuring uniform current distribution without needing to precisely define layout dimensions
Solution Approach 2:
The intermediate metal film acts as an intermediary element that distributes the surge current uniformly to multiple drain regions. Its rectangular ring shape with openings allows it to serve as a current distribution network, ensuring that the ESD protection circuit operates uniformly across all channels without requiring precise layout dimension control
2Reliability
If the first via is arranged only on one side of the intermediate metal film directly above the drain, then the surge current flows uniformly among all drains, but the structural complexity increases
Solution Approach 1:
The patent intentionally uses asymmetric arrangement of the first via (positioned only on one side of the intermediate metal film) to achieve symmetric current distribution. This asymmetric via placement, combined with the rectangular ring-shaped intermediate metal film, creates balanced electrical pathways that ensure uniform surge current flow among all drain regions
3Ease of operation
If the intermediate metal film has a rectangular ring shape with opening under the pad, then the pad can be exposed for connection, but the manufacturing precision requirements increase
Solution Approach 1:
The intermediate metal film is segmented into a rectangular ring shape with openings, which allows the pad to be exposed through the opening for external connection. This segmentation approach separates the current distribution function (ring structure) from the connection function (opening), achieving both goals without requiring high manufacturing precision
Data Source
AI summary
Provided is a semiconductor device having high ESD tolerance. A first via (16) is used for electrically connecting a pad to a drain of an NMOS transistor of an ESD protection circuit. The first via (16) is arranged directly above the drain and present substantially directly under the pad. Consequently, a surge current caused by ESD and applied to the pad is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protection circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device increases.