ESD Protection Structure With Waved Contour Lines
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Solution Overview
Problem
Existing ESD protection structures for semiconductor devices suffer from non-uniform electric field distribution due to curvature variations, leading to vulnerability at corners and limited high-voltage withstanding capacity, which affects the effectiveness of ESD protection.
Innovation Solution
A patterned conductive ESD protection layer with a substantially closed ring shape having waved outer and inner contour lines and a midline with constant curvature, doped with alternately arranged conductivity-type zones, is integrated between the gate and source regions to provide uniform electric field distribution and enhanced current conduction capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional ESD protection structure with straight edges is used, then the manufacturing process is simple, but the electric field distribution is non-uniform and corners are vulnerable to breakdown
Solution Approach 1:
The patent applies curvature by replacing straight edges with arc-shaped edges in the ESD protection structure. Specifically, the first and second ESD protection structures have first and second edges respectively formed as arcs, which distributes the electric field more uniformly along the perimeter and eliminates the concentration of electric field at sharp corners, thereby improving high-voltage withstanding capacity and preventing premature breakdown.
2Reliability
If the perimeter of the ESD protection structure is increased to increase PN junction area, then current conduction capacity is enhanced, but the structure becomes more complex and harder to manufacture
Solution Approach 1:
The arc-shaped edges increase the perimeter length compared to straight edges, thereby increasing the PN junction area and enhancing current conduction capacity. The arc geometry can be implemented through standard semiconductor fabrication processes using curved layout patterns, maintaining manufacturing feasibility while achieving improved electrical performance.
Solution Approach 2:
The patent applies different geometric characteristics to different parts of the ESD protection structure. The arc-shaped edges are applied specifically at the corners and along the perimeter where electric field concentration occurs, while the overall structure maintains a simple rectangular or square footprint. This localized application of curvature optimizes the critical regions without complicating the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the breakdown voltage and current conduction uniformity of the ESD protection structure, reducing the likelihood of breakdown and enhancing the high-voltage withstanding capacity by ensuring uniform electric field distribution across the PN diodes.
Implementation Method 1
an ESD protection module is coupled between a gate and a source of the semiconductor device to protect a gate oxide of such a device from being damaged by ESD. The ESD protection module is configured to provide a conduction path between the source and the gate of the device once a gate to source voltage of the device caused by ESD exceeds an ESD threshold voltage
Implementation Method 2
provide protection structures to a semiconductor device so as to prevent the device from being damaged by a high voltage and/or a high current induced by electro-static discharge (ESD)
Implementation Method 3
electric field distribution in the ESD protection structure is non-uniform. The electric field is more intensive in portions having relatively larger curvature (e.g. at each corner 501) than in portions having relatively smaller curvature (e.g. at each side 502) in the ESD protection structure 50
Implementation Method 4
The ESD protection structure 50 may usually be formed by doping a polysilicon layer 51 with P type and N type dopants so as to form a plurality of alternately arranged P type doped regions 511 and N type doped regions 512 in the polysilicon layer 51
Data Source
AI summary
An ESD protection structure and a semiconductor device having an ESD protection structure with the ESD protection structure including a patterned conductive ESD protection layer. The ESD protection layer is patterned to have a first portion of a substantially closed ring shape having an outer contour line and an inner contour line parallel with each other. The outer and the inner contour lines are waved lines. The first portion further has a midline between and parallel with the outer and the inner contour lines. The midline is a waved line having a substantially constant curvature at each point of the midline. Therefore the ESD protection layer has a substantially uniform curvature and an increased perimeter which advantageously improve the breakdown voltage and the current handling capacity of the ESD protection structure.