eSPI Bus Clock Phase Arbitration for Multi-Slave Expandability
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Solution Overview
Problem
Conventional bus systems, particularly those using the enhanced serial peripheral interface (eSPI) bus, are limited to one-to-one communication mechanisms, which restrict the ability to efficiently schedule and communicate with multiple slave devices, hindering expandability and flexibility.
Innovation Solution
A bus system that includes a master device connected to multiple slave devices via an eSPI bus, where each slave device has a pin connected through a control line for clock signal synchronization and phase adjustment, allowing for synchronized clock signals with phase differences, enabling effective arbitration and communication among multiple slave devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one-to-one communication mechanism is used between chip set and external circuit modules, then communication reliability is improved, but communication efficiency and expandability deteriorate
Solution Approach 1:
The patent segments the communication process by introducing separate arbitration and data transmission phases. The arbitration phase uses the ALERT_HAND line to determine which slave device communicates, while the actual data transmission occurs in dedicated time slots. This segmentation allows multiple slave devices to share the bus efficiently while maintaining reliable one-to-one communication when needed.
Solution Approach 2:
The patent implements periodic arbitration cycles where slave devices take turns attempting to communicate with the master device. Each slave device has a specific time window (determined by clock phase) to assert its communication request on the ALERT_HAND line. This periodic structure enables multiple devices to access the bus systematically, improving overall communication efficiency while preserving reliability.
2Device complexity
If one-to-one communication mechanism is used between chip set and external circuit modules, then communication simplicity is improved, but expandability deteriorates
Solution Approach 1:
The patent makes the ALERT_HAND control line multi-functional. It serves both as an interrupt signal line for traditional one-to-one communication and as an arbitration medium for multi-device communication. By encoding arbitration information in the timing and phase of ALERT_HAND assertions, the system can support both communication modes using the same physical infrastructure, thereby improving expandability without increasing complexity.
3Adaptability or versatility
If multiple slave devices share the same bus, then expandability is improved, but communication coordination difficulty increases
Solution Approach 1:
The patent introduces the ALERT_HAND line as an intermediary for arbitration between multiple slave devices. Instead of requiring complex direct coordination between all pairs of slave devices, each device only needs to interact with the master device through the standardized ALERT_HAND protocol. The master device acts as a central coordinator, simplifying the coordination complexity while enabling multiple devices to share the bus.
Solution Approach 2:
The patent uses clock phase shifting as a parameter change mechanism to differentiate between multiple slave devices. Each slave device is assigned a specific clock phase offset, which determines when it can assert its communication request on the ALERT_HAND line. This parameter-based differentiation allows the system to coordinate multiple devices without requiring complex addressing or identification protocols, maintaining simplicity while enabling expandability.
Data Source
AI summary
A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. The slave devices are electrically connected together via a control line. A first slave device is configured to provide a first clock signal to each second slave device via the control line, so that a second clock signal of each second slave device is synchronized with the first clock signal. After the second clock signals are synchronized with the first clock signal, each second slave device is configured to adjust a phase of the second clock signal in a clock phase shift stage, so that each second clock signal has a phase difference with the first clock signal. The phase differences between the second clock signals of the second slave devices and the first clock signal are different.