Unified eSPI Debug Port for Multi-Chip Low-Power Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Debugging multiple chips in a computer system is complex due to the need for multiple debug ports and synchronization of debug data, which becomes challenging when IO voltage is phased out in advanced chips, especially in low power modes.
Innovation Solution
A unified debug port on a less advanced silicon process chip allows access to debug data from multiple chips using an eSPI bus, enabling debug data transfer even in low power modes, and defining a new transaction type over the eSPI bus for debug data communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple debug ports are used to access debug data from multiple chips, then debug coverage is improved, but device complexity and synchronization difficulty increase
Solution Approach 1:
The patent combines multiple debug data sources from different chips into a single unified debug port interface. The first chip aggregates debug data from multiple components and transmits it through a single eSPI bus interface to the second chip, eliminating the need for multiple separate debug ports while maintaining comprehensive debug coverage.
Solution Approach 2:
The unified debug port on the second chip serves multiple functions: it receives debug data from the first chip, collects local debug data from the second chip's own components, and provides a single access point for external debuggers to interrogate both chips. This multi-functional interface replaces what would traditionally require multiple specialized debug ports.
2Use of energy by moving object
If IO voltage is phased out in advanced chips, then power consumption is reduced, but debug data access capability is lost
Solution Approach 1:
The patent introduces an intermediary communication path using the eSPI bus to transfer debug data. Instead of requiring direct IO voltage connections from the advanced first chip to external debuggers, the eSPI bus acts as an intermediary that can operate at lower voltages suitable for low-power modes, while still enabling full debug data access through the unified debug port on the second chip.
Solution Approach 2:
The debug data is copied from the first chip's internal components through the eSPI bus to the second chip's memory, where it can be accessed externally. This copying mechanism allows the original chip to enter low-power states without losing debug data accessibility, as the data exists in a accessible format at the second chip.
3Device complexity
If a unified debug port is used to access multiple chips, then device complexity is reduced, but data transfer bandwidth may be limited
Solution Approach 1:
The patent segments debug data into different priority levels and types, using virtual channels to organize traffic. High-priority debug data can be transmitted with lower latency, while less critical data can be multiplexed efficiently. This segmentation allows the single eSPI bus to handle multiple debug data streams simultaneously without overwhelming the bandwidth.
Solution Approach 2:
The debug data transfer operates in periodic cycles with defined transmission windows. During these windows, debug data is prioritized and transmitted with guaranteed bandwidth, while during other periods, normal eSPI traffic continues uninterrupted. This periodic scheduling ensures that debug functionality receives adequate bandwidth without permanently dedicating the bus.
Data Source
AI summary
An apparatus comprises a first semiconductor chip comprising a first communication controller to receive first debug data from a second semiconductor chip; a memory to store the first debug data from the second semiconductor chip and second debug data of the first semiconductor chip; and a second communication controller to transmit the first debug data from the second semiconductor chip and the second debug data of the first semiconductor chip to an output port of the first semiconductor chip.