eSPI Packet Encapsulation in PCIe Interconnects

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Solution Overview

Problem

In multi-node computing systems, resource sharing across nodes is costly and power-intensive due to electrical and routing issues, limiting design flexibility and increasing latency.

Innovation Solution

The technique involves tunneling Enhanced Serial Peripheral Interface (eSPI) packets within Peripheral Component Interconnect Express (PCIe) packets, allowing eSPI resources to be shared across nodes via a PCIe interface, eliminating the need for dedicated eSPI interfaces and enabling flexible multi-node topologies with reduced latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If dedicated eSPI interfaces are provided to each node, then resource sharing capability is improved, but system cost and complexity increase

Engineering Contradiction:
Improveresource sharing capabilityVSAvoidsystem cost and complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The PCIe interface is designed to perform multiple functions: it handles both native PCIe communications and encapsulated eSPI packet transmissions. This multi-functionality eliminates the need for separate dedicated eSPI interfaces at each node, reducing system complexity while maintaining resource sharing capability. The conversion logic within nodes enables the PCIe interface to universally handle both protocol types.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

A central component acts as an intermediary that receives encapsulated eSPI packets from multiple nodes via PCIe interfaces, decapsulates them, and forwards to the target eSPI device. This mediator approach allows resource sharing without requiring direct eSPI interface connections at each node, reducing overall system complexity while enabling versatile resource access.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Use of energy by moving object

If resource sharing is implemented across multi-node systems, then power consumption is reduced, but latency increases

Engineering Contradiction:
Improvepower consumptionVSAvoidlatency
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

eSPI packets are nested within PCIe packets, with the eSPI protocol encapsulated inside the PCIe protocol framework. This nesting allows eSPI communications to traverse the PCIe infrastructure, enabling resource sharing across nodes while maintaining efficient packet handling. The encapsulation preserves the original eSPI protocol semantics while leveraging the PCIe transport mechanism.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent replaces direct physical eSPI interface connections with a logical encapsulation mechanism over PCIe. Instead of requiring dedicated electrical interfaces and routing for each eSPI connection, the system uses protocol encapsulation and conversion logic, substituting complex electrical routing with software/firmware-based packet handling that reduces latency while enabling power-efficient resource sharing.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If protocol encapsulation is implemented, then interface flexibility is improved, but processing complexity increases

Engineering Contradiction:
Improveinterface flexibilityVSAvoidprocessing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The packet handling process is segmented into distinct stages: PCIe packet reception, eSPI packet extraction and identification, routing determination, and forwarding. This segmentation of the encapsulation/decapsulation process into manageable steps reduces processing complexity by organizing the workflow into discrete, manageable operations rather than a monolithic complex process.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4216065A1Method, apparatus and system for encapsulating information in a communication
Publication Date: 2023.07.26 INTEL CORP
  • EP4216065A1 patent drawingFigure 1
  • EP4216065A1 patent drawingFigure 2
  • EP4216065A1 patent drawingFigure 3

AI summary

Techniques for communications within a computing system are provided. For example, a system on chip (SoC) comprises: a plurality of cores including a first core and a second core; a cache memory coupled to the plurality of cores; a first host device to receive information from the first core and to include the information in one or more first packets of a first communication protocol; a selection logic coupled to the first host device to receive the one or more first packets and to provide the one or more first packets to a first interface or a conversion logic; the first interface coupled to the selection logic to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic coupled to the selection logic to receive the one or more first packets from the selection logic and to communicate the one or more first packets within one or more second packets of a second communication protocol; and a second interface coupled to the conversion logic to receive the one or more second packets from the conversion logic and to communicate the one or more second packets to a second device via a second interconnect of the second communication protocol.