ESYNC Hybrid Mode Clock Switching for Variable Refresh Displays
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Solution Overview
Problem
Current display processing techniques do not effectively address the characteristics of display panels that support a wide range of variable refresh rates, leading to inefficient power consumption due to the use of high-power phased lock loop (PLL) clocks when lower accuracy and power-efficient resistor-capacitor (RC) oscillator clocks are needed.
Innovation Solution
A method and apparatus that transition the source of a clock from a PLL clock to an RC oscillator clock during changes in refresh rates, conserving power by using the RC oscillator during static displays and maintaining accurate clocking during active frame transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phased lock loop (PLL) clock is used to generate the external HSYNC signal, then accurate clocking and video timing synchronization are maintained, but power consumption increases
Solution Approach 1:
The system dynamically switches between PLL clock and RC oscillator clock based on the refresh rate of the display panel. When the refresh rate changes, the system transitions from using the accurate but power-consuming PLL clock to the power-efficient RC oscillator clock, and vice versa. This dynamic adaptation resolves the contradiction by selecting the appropriate clock source according to operational requirements.
Solution Approach 2:
The invention changes the parameter of clock source selection based on refresh rate conditions. By monitoring refresh rate changes and adjusting the clock generation method accordingly, the system achieves both accurate timing when needed and power efficiency when possible, resolving the trade-off between clock accuracy and power consumption.
2Adaptability or versatility
If the refresh rate of the display panel changes, then power mode transition is triggered, but maintaining continuous HSYNC signal transmission becomes challenging
Solution Approach 1:
The system performs preliminary switching of the clock source before the actual refresh rate change takes effect. By anticipating the need for clock source transition and executing it in advance, the system ensures that the HSYNC signal remains continuous and uninterrupted during refresh rate changes, maintaining both adaptability and reliability.
Solution Approach 2:
The invention uses the HSYNC signal itself as an intermediary to coordinate the transition between different clock sources. The continuous transmission of HSYNC serves as a reference that allows seamless switching between PLL and RC oscillator clocks without disrupting the display synchronization, thus maintaining reliability while enabling refresh rate variability.
Data Source
AI summary
This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for ESYNC hybrid mode. A processor determines that an AP is to transition from a first power mode to a second power mode based on a change in a refresh rate of a display panel. The processor switches, based on the determination and during a transmission of a continuous external HSYNC signal, a source of a clock associated with the external HSYNC signal from being generated via PLL clock to being generated via an RC oscillator clock.