ET Equalizer Circuit for Impedance and Group Delay Compensation
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Solution Overview
Problem
Mobile communication devices experience increased power consumption and thermal dissipation due to distortions in the time-variant ET voltage caused by trace inductance, load impedance, and group delay, particularly when handling high modulation bandwidth RF signals, leading to unwanted distortions in RF signals.
Innovation Solution
An equalizer circuit in an envelope tracking integrated circuit (ETIC) is employed to equalize the target voltage by offsetting inherent impedance and mitigating group delay, generating a processed target voltage to reduce distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the time-variant ET voltage is generated to track the time-variant power envelope of a higher modulation bandwidth RF signal, then the data rate is improved, but distortions caused by trace inductance, load impedance, and group delay increase
Solution Approach 1:
The equalizer circuit performs preliminary processing on the target voltage before it is used to generate the ET voltage. By pre-compensating for impedance and group delay effects in the target voltage signal, the system anticipates and corrects for distortions that would otherwise occur during the voltage tracking process, thereby maintaining accuracy at higher modulation bandwidths
Solution Approach 2:
The equalizer circuit acts as an intermediary between the target voltage generation and the ET voltage generation stages. It processes the target voltage through impedance equalization and group delay mitigation functions, transforming it into a compensated voltage that accounts for trace inductance and load impedance effects, thereby enabling accurate tracking despite these parasitic elements
2Use of energy by moving object
If the ET voltage tracks the power envelope of wide modulation bandwidth RF signals, then the power amplifier efficiency is improved, but distortions in the ET voltage increase due to inherent impedance and group delay
Solution Approach 1:
The equalizer circuit performs preliminary compensation on the target voltage to counteract the effects of inherent impedance and group delay before the ET voltage is generated. This pre-processing ensures that the ET voltage maintains linearity and accurately tracks the power envelope even at wide modulation bandwidths where these effects would otherwise cause significant distortion
Solution Approach 2:
The equalizer circuit implements feedback mechanisms where the characteristics of the ETIC (including its inherent impedance and group delay) are measured or characterized, and this information is used to adjust and equalize the target voltage. This closed-loop approach ensures that the ET voltage remains linear and accurately tracks the RF signal power envelope despite the ETIC's parasitic elements
Data Source
AI summary
An equalizer circuit in an envelope tracking (ET) integrated circuit (ETIC) is disclosed. The ETIC (26) is configured to generate an ET voltage based on a target voltage (VTGT) for amplifying a radio frequency (RF) signal(s). Since the ETIC has inherent impedance and group delay that can cause distortion in the ET voltage, an equalizer circuit (24) is provided in the ETIC to equalize the target voltage prior to generating the ET voltage. Specifically, the equalizer circuit generates an equalized target voltage to offset the inherent impedance and a modified target voltage to mitigate the group delay. Accordingly, the equalizer circuit can output a processed target voltage, which can include the equalized target voltage and/or the modified target voltage, for generating the ET voltage. As a result, it is possible to reduce distortion resulted from the inherent impedance and group delay, especially when the RF signal(s) is modulated in a wide modulation bandwidth.