ET Equalizer Circuit for Impedance and Group Delay Compensation
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Solution Overview
Problem
Existing envelope tracking (ET) systems in mobile communication devices experience distortions in ET voltage due to trace inductance, load impedance, and group delay, particularly when operating at high modulation bandwidths, leading to inefficiencies and performance degradation.
Innovation Solution
An equalizer circuit is integrated into the ET integrated circuit (ETIC) to equalize the target voltage prior to generating the ET voltage, offsetting inherent impedance and mitigating group delay, thereby reducing distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the ET voltage is generated to track the time-variant power envelope of a high modulation bandwidth RF signal, then the data rate is improved, but voltage distortions occur due to trace inductance, load impedance, and group delay
Solution Approach 1:
The equalizer circuit performs preliminary processing on the target voltage before it is used to generate the ET voltage. By pre-equalizing the target voltage to compensate for anticipated impedance and group delay effects, the system proactively counteracts distortions before they occur in the voltage tracking process, thereby maintaining voltage accuracy while enabling high data rates
Solution Approach 2:
The equalizer circuit acts as an intermediary component between the target voltage source and the ET voltage generator. This intermediate processing stage modifies the target voltage to pre-compensate for distortions that would otherwise occur in the ETIC, serving as a mediator that resolves the conflict between high-speed operation and voltage accuracy
2Productivity
If the modulation bandwidth is increased to achieve higher data rates, then the productivity is improved, but the voltage distortions due to group delay and impedance are exacerbated
Solution Approach 1:
The equalizer circuit applies preliminary anti-action by pre-compensating the target voltage with equalization factors that counteract the expected distortions from trace inductance, load impedance, and group delay. This preemptive compensation neutralizes harmful effects before they can degrade the ET voltage, enabling high bandwidth operation without sacrificing voltage accuracy
3Reliability
If the ET voltage tracks the power envelope with high fidelity to improve power amplifier linearity, then the efficiency is improved, but the complexity of the voltage generation circuit increases
Solution Approach 1:
The equalizer circuit serves as an intermediary processing stage that enhances voltage tracking fidelity without requiring fundamental changes to the ETIC architecture. By inserting this intermediate equalization stage, the system achieves improved power amplifier linearity while adding only moderate complexity through a dedicated equalization module rather than redesigning the entire voltage generation system
Data Source
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AI summary
An equalizer circuit in an envelope tracking (ET) integrated circuit (ETIC) is disclosed. The ETIC (26) is configured to generate an ET voltage based on a target voltage (VTGT) for amplifying a radio frequency (RF) signal(s). Since the ETIC has inherent impedance and group delay that can cause distortion in the ET voltage, an equalizer circuit (24) is provided in the ETIC to equalize the target voltage prior to generating the ET voltage. Specifically, the equalizer circuit generates an equalized target voltage to offset the inherent impedance and a modified target voltage to mitigate the group delay. Accordingly, the equalizer circuit can output a processed target voltage, which can include the equalized target voltage and/or the modified target voltage, for generating the ET voltage. As a result, it is possible to reduce distortion resulted from the inherent impedance and group delay, especially when the RF signal(s) is modulated in a wide modulation bandwidth.