Etch-Aware Metrology Mark Design for Overlay Accuracy

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Solution Overview

Problem

Existing lithographic processes face challenges in accurately reproducing small features due to microloading effects and chemical sensitivity during the etching process, leading to variations in critical dimensions and overlay errors in metrology marks.

Innovation Solution

A method is developed to simulate the etch process, considering pattern density, microloading effects, and etch chemistry sensitivity, to optimize metrology mark design and placement, reducing intra-mark and intra-die overlay variations through computational simulations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional lithographic processes are used to pattern small features, then manufacturing complexity is reduced, but manufacturing precision deteriorates due to microloading effects and chemical sensitivity during etching

Engineering Contradiction:
Improvecritical dimension accuracyVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing computational simulations of the etch process before actual fabrication. The methodology predicts etch-induced variations in critical dimensions and overlay by modeling microloading effects and chemical sensitivity, allowing optimization of metrology mark design and placement parameters in advance to minimize these variations before manufacturing begins

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses computational simulations as a virtual copy of the physical etch process. By creating a digital model that replicates etch chemistry, pattern density effects, and microloading phenomena, the system can predict and optimize outcomes without repeatedly performing physical trial-and-error experiments, thus improving precision while managing complexity

Inventive Principle:
Principle #26Copying

2Measurement precision

If standard metrology mark designs are used, then ease of manufacture is improved, but measurement precision deteriorates due to etch-induced intra-mark and intra-die overlay variations

Engineering Contradiction:
Improveoverlay measurement accuracyVSAvoidmetrology mark design simplicity
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent applies local quality by optimizing metrology mark design parameters specifically in regions affected by microloading effects. The computational methodology identifies areas with high pattern density variations and adjusts metrology mark dimensions, shapes, or placements locally in these critical zones, while leaving other areas with standard designs unchanged, thus improving measurement precision without unnecessarily complicating the overall manufacturing process

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs parameter changes by systematically varying metrology mark design parameters (such as critical dimensions, spacing, and placement coordinates) based on simulation results. The methodology identifies optimal parameter values that compensate for predicted etch-induced variations, transforming standard designs into optimized versions that maintain ease of manufacture while significantly improving overlay measurement accuracy

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250284215A1Systems and methods for optimizing metrology marks
Publication Date: 2025.09.11 ASML NETHERLANDS BV
  • US20250284215A1 patent drawing
  • US20250284215A1 patent drawing
  • US20250284215A1 patent drawing

AI summary

Systems, methods, and computer software are disclosed for optimizing a metrology mark. One method includes simulating an etch process based on one or more selected from: a pattern density, a microloading effect induced intra-mark variation, or a sensitivity of intra-mark variation to etch chemistry. The method can predict etch-induced process effects on the metrology mark based on the simulation of the etch process and optimize the metrology mark based on the predicted etch-induced process effects.