Etch Blocking Layer for Semiconductor Electrode Protection

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Solution Overview

Problem

The manufacturing of Micro Metal Sphere (MEMS) devices faces challenges in achieving reliable switching operations and optimal manufacturing yield due to the instability of the upper electrode pattern and the susceptibility of the semiconductor device to etching, which affects the reliability and yield of the devices.

Innovation Solution

A method involving the formation of an etch blocking layer on the upper electrode pattern, which is made of conductive materials like tungsten, to protect the electrodes from etching, combined with a specific etching process using diluted HF and Buffered HF, to create a cavity exposing the etch stop film and allowing for the formation of a contact ball, thereby enhancing the reliability and yield of the semiconductor device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If wet etching is used to form cavities, then manufacturing efficiency is improved, but the upper electrode pattern is damaged by etchant exposure leading to reduced reliability

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidswitching reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

An etch blocking layer is introduced as an intermediary protective barrier between the etchant and the upper electrode pattern. This layer is positioned on the side of the upper electrode and extends into the cavity region, allowing wet etching to proceed while preventing direct contact between etchant and the electrode, thus resolving the contradiction between manufacturing efficiency and switching reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The etch blocking layer is formed in advance before the wet etching process. By pre-positioning this protective layer on the upper electrode side, the electrode is already shielded against etchant damage when the etching begins, enabling aggressive etching conditions to be used without compromising electrode integrity or device reliability

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If the upper electrode pattern is made more flexible with greater degrees of freedom, then design adaptability is improved, but manufacturing precision becomes more difficult to control

Engineering Contradiction:
Improveupper electrode pattern flexibilityVSAvoidelectrode pattern precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The etch blocking layer serves as a protective intermediary that enables the upper electrode pattern to have greater design freedom without compromising manufacturing precision. By shielding the electrode during etching, it allows for more flexible pattern configurations while maintaining controlled manufacturing processes

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

By forming the etch blocking layer beforehand, the patent enables greater adaptability in upper electrode pattern design while maintaining manufacturing precision. The pre-positioned protective layer allows engineers to optimize electrode configurations without fearing etchant-induced variations, thus decoupling design flexibility from manufacturing precision concerns

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9156681B2Semiconductor device and method for manufacturing the same
Publication Date: 2015.10.13 DONGBU HITEK CO LTD
  • US9156681B2 patent drawing
  • US9156681B2 patent drawing
  • US9156681B2 patent drawing

AI summary

Method for manufacturing a semiconductor device includes the steps of forming a lower electrode pattern on a substrate, forming a first interlayer insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first interlayer insulating layer, forming a second interlayer insulating layer on the upper electrode pattern, forming an etch blocking layer on a side of the upper electrode pattern, wherein the etch blocking layer passes through the first interlayer insulating layer, forming a cavity which exposes the side of the etch blocking layer by etching the second interlayer insulating layer, and forming a contact ball in the cavity.