Etch Buffer Layer for Self-Aligned Trench Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional lithography techniques face challenges in forming small trench dimensions due to high costs and poor critical dimension uniformity, often requiring large etching biases and misalignment compensation, which can result in gate shorting.
Innovation Solution
The method involves forming an etch buffer layer with a narrower upper edge width than lower edge width, combined with a hard mask layer having a single opening, to achieve partial self-alignment and selective etching, allowing for the formation of smaller trench dimensions with improved uniformity and reduced etch bias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography is used to form small trench dimensions, then high cost exposure tools are required, but manufacturing precision deteriorates due to poor critical dimension uniformity
Solution Approach 1:
The patent introduces an etch buffer layer as an intermediary element between the gate structure and the trench formation process. This buffer layer with its specific etch rate enables precise trench dimension control without requiring advanced lithography tools, thereby improving manufacturing precision while reducing manufacturing complexity
Solution Approach 2:
The patent changes the etch rate parameter of the buffer layer to achieve selective etching. By controlling the etch rate of the buffer layer to be slower than the interlayer dielectric layer, the process achieves precise critical dimension uniformity without requiring expensive EUV lithography tools
2Manufacturing precision
If large etching bias is used to compensate for lithographic pattern, then trench formation is achieved, but gate shorting occurs due to misalignment
Solution Approach 1:
The etch buffer layer provides self-alignment functionality during the etching process. The buffer layer's selective etching characteristics automatically define the trench position and dimensions, eliminating the need for large etching bias compensation and preventing gate shorting from misalignment
Solution Approach 2:
The buffer layer is formed in advance with specific geometric characteristics (narrower upper edge width than lower edge width) that pre-determine the final trench dimensions. This preliminary structuring enables precise trench formation without requiring aggressive etching that could cause misalignment and gate shorting
3Length of moving object
If advanced lithography tools are used, then small trench dimensions can be formed, but manufacturing cost increases
Solution Approach 1:
The patent changes the etch rate parameter of the buffer layer to achieve selective etching, enabling small trench dimensions to be formed using conventional lithography tools instead of expensive advanced tools, thereby reducing manufacturing cost while maintaining small trench size capability
Solution Approach 2:
The buffer layer acts as an intermediary that enables conventional lithography tools to achieve the precision normally requiring advanced tools. The buffer layer's controlled etching behavior compensates for the limitations of conventional lithography, allowing small trench formation at lower cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of smaller trench dimensions with improved critical dimension uniformity, reduced etch bias, and increased manufacturing flexibility, while relaxing lithography tool constraints and lowering costs.
Implementation Method 1
etching the dielectric material layer to form a plurality of trenches using the mask layer and the etch buffer layer as an etch mask
Data Source
AI summary
Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask.