Etch Isolation Structure for MEMS 3D IC Integration
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Solution Overview
Problem
During the manufacturing of 3D integrated circuits (ICs), the bonding process between MEMS and CMOS ICs can cause cracks in the barrier layer, allowing release etches to propagate and damage the CMOS IC, leading to performance issues and reduced yield due to undesired etching.
Innovation Solution
Incorporating an etch isolation structure beneath the CMOS IC surface, which includes inner and outer anchors and sidewalls to isolate and limit the extent of over-etching to sacrificial regions, thereby preventing damage from release etches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bonding process is performed between MEMS and CMOS ICs, then 3D IC integration is achieved, but cracks form in the barrier layer allowing release etch to propagate and damage the CMOS IC
Solution Approach 1:
The patent applies preliminary action by forming etch isolation structures and sacrificial regions before the bonding process. These structures are prepared in advance to prevent etch propagation that would occur after bonding creates cracks in the barrier layer.
Solution Approach 2:
The patent introduces etch isolation structures as intermediary elements between the barrier layer and the CMOS IC substrate. These structures act as mediators that intercept and contain the release etch, preventing it from reaching and damaging the CMOS IC devices.
2Ease of manufacture
If release etch is applied to remove sacrificial material, then MEMS device release is achieved, but etch propagates through barrier layer cracks and damages CMOS IC
Solution Approach 1:
The patent applies local quality by creating localized etch isolation structures with different etch resistance properties in specific regions. The sacrificial regions are locally modified to be more etch-resistant, containing the harmful etch propagation to specific areas while allowing MEMS release in other regions.
Solution Approach 2:
The patent converts the harmful release etch into a beneficial process by using it to selectively remove the sacrificial regions that have been designed to be etch-vulnerable. The etch that would normally damage the CMOS IC is redirected to remove only the intended sacrificial material within isolated regions.
3Object-affected harmful factors
If barrier layer is made thin to protect CMOS IC, then protection is provided, but bonding force creates cracks more easily
Solution Approach 1:
The patent transitions from a two-dimensional thin barrier layer to a three-dimensional etch isolation structure system. By adding vertical depth and creating enclosed sacrificial regions, the solution provides etch protection through a different dimensional approach rather than relying solely on thin-film barrier properties.
Solution Approach 2:
The patent segments the barrier layer protection function into multiple components: the original barrier layer for general protection, and additional etch isolation structures with sacrificial regions for localized etch containment. This segmentation allows each component to perform its specific function without compromising the other.
4Reliability
If etch isolation structures are added to contain release etch, then CMOS IC protection is improved, but device complexity increases
Solution Approach 1:
The etch isolation structures serve multiple functions: they contain release etch propagation, define sacrificial region boundaries, and provide mechanical support during processing. This multi-functionality reduces the need for additional separate structures, offsetting the complexity increase with functional consolidation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The etch isolation structure effectively confines the release etch to predetermined sacrificial regions, minimizing damage to the CMOS IC and enhancing the manufacturing yield and performance of 3D ICs by preventing unwanted etching.
Implementation Method 1
a release etch, such as a vapor hydrofluoric (vHF) etch, is used to remove the sacrificial MEMS material
Data Source
AI summary
A three-dimensional (3D) integrated circuit (IC) includes a first IC and a second IC. The first IC includes a MEMS device and a first bonding structure. The second IC includes a second bonding structure. The first and second bonding structures are bonded together to couple the first IC to the second IC. A conformal barrier layer is disposed over a surface of the second IC nearest the first IC. An etch isolation structure is arranged beneath the surface of the second IC and encloses a sacrificial region which is arranged on either side of the second bonding structure and which is arranged in the second IC.