3D Memory Contact Formation with Etch-Rate-Tuned Insulating Layers
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Solution Overview
Problem
Existing semiconductor devices, particularly 3D memory devices, face challenges in forming consistent contact structures across multiple decks of conductive layers due to varying etching rates and depths, leading to potential short circuits and increased manufacturing complexity.
Innovation Solution
The implementation of an insulating structure with varying etching rates and thicknesses to control the formation of contact structures, allowing them to extend through specific portions of the insulating layer without penetrating conductive layers, thereby simplifying the manufacturing process and reducing the risk of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If contact structures extend through multiple decks of conductive layers to increase connectivity, then the device functionality is improved, but the risk of short circuits and manufacturing complexity increases
Solution Approach 1:
The patent introduces an insulating layer as an intermediary between conductive layers to control contact structure formation. This mediator layer with specific etching rate allows contact structures to extend through selected conductive layers while preventing penetration into adjacent conductive layers, thereby enabling connectivity without short circuits.
Solution Approach 2:
The insulating layer is configured with varying thickness across different regions (first portion thicker than second portion), creating local quality differences. This allows contact structures to have different lengths in different areas, enabling selective connectivity to specific conductive layers while maintaining isolation elsewhere.
2Adaptability or versatility
If contact structures extend through all conductive layers to maximize connectivity, then the device functionality is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent changes the etching rate parameter by selecting an insulating layer material with a specific etching rate that is lower than adjacent conductive layers. This parameter difference automatically limits contact structure penetration depth, reducing manufacturing precision requirements while maintaining controlled connectivity.
Solution Approach 2:
The insulating layer is formed beforehand with predetermined thickness variations before contact hole etching. This preliminary action pre-establishes the depth limits for contact structures, allowing standard etching processes to produce precise results without requiring complex real-time control.
3Ease of manufacture
If uniform insulating layer thickness is used to simplify manufacturing, then the manufacturing complexity is reduced, but the ability to control contact structure lengths decreases
Solution Approach 1:
The insulating layer is segmented into portions with different thicknesses (first portion and second portion) to provide different levels of protection. This segmentation allows the layer to be formed using standard processes while still achieving differentiated contact structure lengths through selective etching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable contact structures in 3D memory devices with reduced manufacturing complexity and cost, improving the electrical performance and reliability of the devices.
Implementation Method 1
A material of the first layer has a first etching rate smaller than an etching rate of an insulating material between the conductive layers
Data Source
AI summary
The present disclosure relates to semiconductor devices and fabrication methods thereof. An example semiconductor device includes conductive layers. The conductive layers include a first conductive layer and a second conductive layer. The semiconductor device further includes an insulating structure over the first conductive layer and the second conductive layer. The insulating structure includes a first layer. A material of the first layer has a first etching rate smaller than an etching rate of an insulating material between the conductive layers. The semiconductor device further includes a first contact structure extending through a first portion of the first layer and connected to the first conductive layer. The semiconductor device further includes a second contact structure extending through a second portion of the first layer and connected to the second conductive layer.