Etch Resistant Fill Control Topographical Features for Directed Self-Assembly
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Solution Overview
Problem
In integrated circuit fabrication, directed self-assembly techniques face challenges in achieving uniformity when filling confinement wells with block copolymers, particularly in areas with lower density of topographical features, leading to potential overfilling and unintended electrical connections.
Innovation Solution
The formation of etch resistant fill control topographical features that define confinement wells, alongside graphoepitaxy features, to direct block copolymers into specific phases, preventing overfilling by obstructing the formation of etchable features in certain areas, thus preventing unintended connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional confinement wells are added to lower density areas to increase local density, then process uniformity is improved, but device complexity increases due to unintended electrical connections
Solution Approach 1:
The patent applies local quality by creating different types of topographical features with different functions: fill control features (non-periodic) in lower density areas to prevent overfilling, and confinement well features (periodic) in higher density areas for normal operation. This spatial differentiation of feature types allows uniform BCP filling across the substrate without creating unintended connections.
Solution Approach 2:
The patent introduces fill control topographical features as intermediary elements that mediate between the BCP deposition process and the confinement wells. These intermediary features obstruct BCP flow and prevent overfilling in lower density areas, acting as a buffer that enables uniform processing without requiring additional confinement wells that would create unintended connections.
2Reliability
If block copolymer is deposited to fill confinement wells, then self-assembly pattern formation is achieved, but overfilling occurs in lower density areas causing unintended connections
Solution Approach 1:
The patent applies preliminary anti-action by placing fill control topographical features in lower density areas before BCP deposition. These features create preliminary obstruction that counteracts the natural tendency of BCP to overfill in lower density areas, preventing the harmful effect of overfilling before it occurs during the deposition process.
3Manufacturing precision
If uniform thickness of BCP is deposited, then process uniformity is improved, but overfilling occurs in lower density areas between topographical features
Solution Approach 1:
The patent uses local quality by implementing different topographical feature types in different spatial regions: fill control features in lower density areas to prevent overfilling, and standard confinement well features in higher density areas. This allows uniform BCP thickness deposition across the entire substrate while accommodating local variations in feature density through region-specific feature design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform filling of confinement wells and prevents the formation of additional openings in the substrate, maintaining process uniformity and avoiding unintended electrical connections between layers.
Implementation Method 1
by annealing the DSA polymers, the A polymer chains and the B polymer chains undergo phase separation to form an A polymer region and a B polymer region that are registered to the guide pattern
Implementation Method 2
One DSA technique is graphoepitaxy in which self-assembly is directed by topographical features that are formed overlying a semiconductor substrate
Data Source
AI summary
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming etch resistant fill control topographical features that overlie a semiconductor substrate. The etch resistant fill control topographical features define an etch resistant fill control confinement well. A block copolymer is deposited into the etch resistant fill control confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant fill control topographical features direct the etch resistant phase to form an etch resistant plug in the etch resistant fill control confinement well.