Semiconductor Interconnection Structure With Etch-Selective Hardmask
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving reliable and durable interconnection structures due to limitations in etch selectivity and fabrication complexity, leading to issues such as warpage and not-open problems during the etching process.
Innovation Solution
The proposed solution involves a stacked interconnection structure with dielectric and hardmask patterns, where the hardmask patterns are made of dielectric materials with controlled density and composition, providing excellent etch selectivity and simplifying the fabrication process by eliminating the need for separate removal steps, thus enhancing reliability and mechanical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used with traditional hardmask materials, then etching can be performed, but etch selectivity is insufficient leading to not-open problems and warpage
Solution Approach 1:
The patent changes the material parameters of the hardmask layer by using dielectric materials with different densities (first density for lower hardmask, second density for upper hardmask). This parameter change enables sufficient etch selectivity between the hardmask layer and dielectric layers, preventing not-open problems while maintaining fabrication process simplicity.
Solution Approach 2:
The patent employs composite material structure where the hardmask layer is formed of dielectric materials with controlled density variations. The lower hardmask has first density and the upper hardmask has second density different from the first, creating a composite structure that provides both etch selectivity and mechanical stability to prevent warpage.
2Ease of manufacture
If traditional interconnection structures are used, then fabrication can proceed, but warpage occurs during etching process
Solution Approach 1:
The patent modifies the density parameters of the hardmask layer to match or exceed the density of the underlying dielectric layer. This parameter adjustment ensures that the hardmask layer has sufficient mechanical strength to prevent warpage during etching while maintaining ease of fabrication through standard deposition processes.
Solution Approach 2:
The patent creates a composite structure where the hardmask layer uses dielectric materials with optimized density characteristics. The lower hardmask (first density) and upper hardmask (second density) form a composite that provides both structural stability to prevent warpage and appropriate etch selectivity, without complicating the fabrication process.
3Productivity
If hardmask layer density is not optimized, then fabrication is simpler, but etching dispersion increases reducing yield
Solution Approach 1:
The patent optimizes the density parameter of the hardmask layer to be greater than or equal to the dielectric layer density. This parameter optimization reduces etching dispersion by ensuring uniform etch rates across the pattern, thereby improving manufacturing precision and increasing overall yield without adding fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved reliability and mechanical stability of the interconnection structure, reducing warpage and fabrication complexity, and enhancing the yield of semiconductor packages with better process control and reduced etching dispersion.
Implementation Method 1
The first hardmask pattern may include a dielectric material having an etch selectivity with respect to the first dielectric layer
Data Source
AI summary
Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.