Etch Selective Protection Layer for Semiconductor Insulation Integrity

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving reliable performance due to issues with the stability and reliability of thin film transistors, particularly in display devices where thin film transistors are used for controlling pixels, leading to potential short circuits and leakage currents.

Innovation Solution

A semiconductor device manufacturing method involving the formation of crystalline and oxide semiconductor patterns with specific etch selectivity, where a protection layer with a different etch rate is used between the insulation layers to prevent damage during etching processes, ensuring the stability of the insulation layers and reducing the risk of short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a protection layer with different etch selectivity is introduced between insulation layers, then the reliability and integrity of insulation layers are improved, but the device structure and manufacturing process become more complex

Engineering Contradiction:
Improveinsulation layer integrityVSAvoidlayer structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A protection layer comprising a metal oxide is introduced as an intermediary layer between the first insulation layer and the second insulation layer. This protection layer serves as a mediator that prevents direct contact and potential short circuits between the two insulation layers, while also providing etch selectivity control during manufacturing processes. The metal oxide material specifically protects the insulation layers from damage during etching operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulation structure is segmented into multiple distinct layers: a first insulation layer, a protection layer in between, and a second insulation layer. This segmentation allows each layer to perform its specific function independently - the first and second insulation layers provide electrical isolation, while the intermediate protection layer provides mechanical protection and etch selectivity. The segmentation resolves the contradiction by distributing complexity across multiple specialized layers rather than requiring a single complex layer.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If thin film transistors are used for controlling pixels in display devices, then the device functionality is improved, but the risk of short circuits and leakage currents increases

Engineering Contradiction:
Improvepixel control functionalityVSAvoidshort circuit resistance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The protection layer acts as an intermediary barrier between the first and second insulation layers that are associated with different thin film transistor structures. By preventing direct contact between these insulation layers, the protection layer eliminates potential leakage paths and short circuit routes, thereby maintaining the reliability required for pixel control functionality while allowing the thin film transistors to operate correctly.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If etching processes are used to define channel regions, then the manufacturing precision is improved, but the risk of damaging insulation layers increases

Engineering Contradiction:
Improvechannel region definitionVSAvoidinsulation layer damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The protection layer serves as a protective intermediary during etching processes. When etching gases are used to define channel regions in the semiconductor layers, the protection layer acts as a barrier that prevents the etching chemicals from damaging the adjacent insulation layers. This allows precise channel region definition through etching while protecting the insulation layers from harmful etching effects.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protection layer introduces etch selectivity parameter control into the manufacturing process. By selecting a metal oxide material with specific etch resistance properties, the process parameters are optimized such that the etching gas selectively removes material from the semiconductor layers to define channels while leaving the protection layer and insulation layers intact. This parameter change enables precise manufacturing without damage.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances the reliability of semiconductor devices by maintaining the integrity of insulation layers, reducing leakage currents, and improving the on/off properties of transistors, thereby ensuring improved performance and longevity.

Implementation Method 1

The pre protection layer includes a material with a first etch selectivity that is different from a second etch selectivity of the pre second insulation layer with respect to an etching gas

Methodology Applied
Scientific EffectEtch selectivity:

Implementation Method 2

patterning the pre second insulation layer using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS11430847B2Crystalline semiconductor and oxide semiconductor thin-film transistor device and method of manufacturing the same
Publication Date: 2022.08.30 SAMSUNG DISPLAY CO LTD
  • US11430847B2 patent drawing
  • US11430847B2 patent drawing
  • US11430847B2 patent drawing

AI summary

A method of manufacturing a semiconductor device. A pre first semiconductor pattern having a crystalline semiconductor material is formed on a base substrate. A pre first insulation layer is formed on the pre first semiconductor pattern. A first semiconductor pattern is formed by defining a channel region in the pre first semiconductor pattern. A pre protection layer is formed on the pre first insulation layer. A pre second semiconductor pattern including an oxide semiconductor material is formed on the pre protection layer. A pre second insulation layer is formed on the pre second semiconductor pattern. The pre second insulation layer is patterned using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed. A second semiconductor pattern is formed by defining a channel region in the pre second semiconductor pattern. The pre protection layer has a material with a first etch selectivity that is different from a second etch selectivity of the second insulation layer with respect to the etching gas.