Dielectric Etch Stop Layer for Shorter Backside Power Vias
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in efficiently routing signals due to the complexity of interconnect structures, particularly in achieving optimal aspect ratios for metal via structures.
Innovation Solution
The use of a dielectric etch stop layer with superb etch selectivity against crystalline silicon and thermal stability, allowing for a uniform thickness that reduces the total height of silicon fins, thereby improving metal via aspect ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the total height of silicon fin is reduced to improve metal via aspect ratio, then metal via aspect ratio is improved, but the fin height is reduced
Solution Approach 1:
The silicon fin structure is segmented into multiple portions along its height, with different etch stop layers positioned at different depths. This allows independent control of etching at different levels, enabling the fin to maintain adequate height for device performance while the upper portions are reduced to improve metal via aspect ratio.
Solution Approach 2:
Etch stop layers are introduced as intermediary structures between the silicon fin and the metal via. These layers selectively prevent etching at specific depths, allowing precise control over the fin height reduction process while protecting critical portions of the fin from being etched away.
2Manufacturing precision
If etch stop layers are used to control fin height, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Different etch stop layers with different etch selectivities are applied at different locations along the fin height. This local differentiation allows precise control of etching at specific levels while maintaining simplicity in other regions, reducing the need for complex uniform structures throughout.
Solution Approach 2:
The etch selectivity parameter is varied across different etch stop layers to achieve differential etching. By changing the material composition and corresponding etch resistance at different heights, the process achieves high precision fin height control using relatively simple deposition and etching steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the aspect ratio of metal via structures, leading to improved performance and efficiency in semiconductor manufacturing by allowing for shorter metal vias and maintaining thermal stability.
Implementation Method 1
a dielectric etch stop layer that exhibits a superb etch selectivity against crystalline silicon
Implementation Method 2
is thermally stable so it will not diffuse into a silicon substrate
Data Source
AI summary
A semiconductor structure includes a first semiconductor fin disposed on a first source/drain region of a first nanosheet transistor device, a second semiconductor fin disposed on a second source/drain region of a second nanosheet transistor device, a first dielectric etch stop layer disposed on the first semiconductor fin, and a second dielectric etch stop layer disposed on the second semiconductor fin. The first semiconductor fin and the second semiconductor fin are of a uniform height.