Etch Stop Layer for Uniform Bit Line Formation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In flash memory systems, the close proximity of bit lines leads to capacitive coupling issues due to their close spacing, making it challenging to form uniform low resistance conductive lines efficiently.

Innovation Solution

The process involves forming contact plugs that extend above an etch stop layer, depositing dielectric layers, and creating trenches of uniform depth to form bit lines with uniform height, optionally removing dielectric material to create air gaps between bit lines, which are then capped to reduce capacitive coupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If bit lines are formed in close proximity to increase density, then productivity and area utilization are improved, but capacitive coupling between bit lines increases causing manufacturing and operational issues

Engineering Contradiction:
Improvememory array densityVSAvoidcapacitive coupling
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

An air gap is introduced as an intermediary medium between adjacent bit lines. This air gap acts as a mediator that reduces the capacitive coupling between bit lines while allowing them to remain in close proximity, thus maintaining high density without the harmful capacitive effects

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric material is selectively removed only in the regions between bit lines to create localized air gaps. This local modification provides reduced capacitive coupling exactly where needed (between bit lines) while maintaining the overall close-proximity layout for high density

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If trenches are etched through multiple dielectric layers to form bit lines, then uniform bit line height and low resistance are achieved, but process complexity increases

Engineering Contradiction:
Improvebit line uniformityVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

An etch stop layer is deposited beforehand as a reference plane before etching the trenches. This preliminary action ensures that all trenches are etched to a uniform depth that exposes the contact plugs, achieving consistent bit line height and low resistance without complex depth control

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch stop layer serves a dual function: it acts as both a structural layer in the dielectric stack and as a self-referencing etch termination plane. The etching process automatically stops at this layer, providing self-regulation of trench depth and eliminating the need for complex external depth control mechanisms

Inventive Principle:
Principle #25Self-service

3Manufacturing precision

If contact plugs extend above the etch stop layer, then uniform trench depth and bit line height are achieved, but additional processing steps are required

Engineering Contradiction:
Improvetrench depth uniformityVSAvoidcontact plug formation complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

Contact plugs are formed to extend above the etch stop layer before the trench etching process. This preliminary action ensures that when trenches are etched to expose the contact plugs, the exposure is uniform across all trenches, achieving consistent bit line formation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch stop layer creates a common reference plane (equipotential surface in terms of etch depth) for all trench etching operations. By having contact plugs extend above this uniform reference plane, the etching process can uniformly expose all contact plugs at the same depth, ensuring uniform bit line height and simplifying the overall manufacturing precision

Inventive Principle:
Principle #12Equipotentiality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method ensures the formation of uniform bit lines with reduced capacitive coupling, improving memory operation by maintaining low resistance and efficient connectivity between bit lines.

Implementation Method 1

trenches are etched to a uniform depth that exposes the contact plugs by using the etch stop layer as a reference plane

Methodology Applied
Scientific EffectEtch stop layer mechanism:

Implementation Method 2

removing dielectric material to create air gaps between bit lines, which are then capped to reduce capacitive coupling

Methodology Applied
Scientific EffectCapacitive coupling reduction: Capacitance

Data Source

PatentUS9847249B2Buried etch stop layer for damascene bit line formation
Publication Date: 2017.12.19 SANDISK TECHNOLOGIES LLC
  • US9847249B2 patent drawing
  • US9847249B2 patent drawing
  • US9847249B2 patent drawing

AI summary

A stack of layers is formed that includes first, second, and third dielectric layers. Contact plugs are then formed extending through the stack. Then a fourth dielectric layer is formed over the stack and contact plugs and trenches are formed through the fourth and third dielectric layers, extending to the second dielectric layer and exposing contact plugs.