Etch Stop Dielectric Layer for Memory Contact Via Planarization
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Solution Overview
Problem
The increasing density of memory cells in semiconductor memory devices leads to challenges in forming contact via structures, resulting in overetching or underetching of dielectric matrix layers, which can cause electrical shorts or opens, due to variations in height and shrinking lateral dimensions.
Innovation Solution
An etch stop dielectric layer is formed to serve as a planarization stopping material and etch stop layer during the formation of contact via structures, ensuring accurate planarization and preventing overetching or underetching by acting as a self-aligned etch stop structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell density is increased, then productivity is improved, but manufacturing precision deteriorates due to overetching or underetching of dielectric matrix layers
Solution Approach 1:
An etch stop dielectric layer is formed over the dielectric matrix layer before contact via structure formation. This preliminary layer serves as a stopping point during etching operations, preventing overetching into the dielectric matrix layer and ensuring precise etch depth control as memory cell density increases
Solution Approach 2:
The etch stop dielectric layer acts as an intermediary between the contact via structure etch process and the underlying dielectric matrix layer. It provides a controlled interface that prevents direct etching into the matrix layer, thereby maintaining manufacturing precision during high-density memory cell fabrication
2Productivity
If lateral dimensions are shrunk to increase density, then productivity is improved, but manufacturing precision deteriorates due to height variations causing etch control issues
Solution Approach 1:
The etch stop dielectric layer is deposited in advance to create a uniform planarization surface. This preliminary action compensates for underlying height variations, providing a consistent starting point for subsequent etching operations and ensuring uniform etch depth across shrunk lateral dimensions
Solution Approach 2:
The introduction of the etch stop dielectric layer changes the etching parameters by providing a distinct material interface with different etch selectivity. This parameter change allows for precise control of etch depth and rate, maintaining manufacturing precision even as lateral dimensions are reduced to increase density
Data Source
AI summary
Each memory cell in an array includes a vertical stack that comprises a bottom electrode, a memory element, and a top electrode. An etch stop dielectric layer is formed over the array of memory cells. A first dielectric matrix layer is formed over the etch stop dielectric layer. The top surface of the first dielectric matrix layer is raised in a memory array region relative to a logic region due to topography. The first dielectric matrix layer is planarized by performing a chemical mechanical planarization process using top portions of the etch stop dielectric layer. A second dielectric matrix layer is formed over the first dielectric matrix layer. Metallic cell contact structures are formed through the second dielectric matrix layer on a respective subset of the top electrodes over vertically protruding portions of the etch stop dielectric layer that laterally surround the array of vertical stacks.