Etch-Stop Film for 3D Memory Word Line Contacts
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Solution Overview
Problem
The challenge in fabricating three-dimensional (3D) memory devices is the complexity and cost associated with forming electrical connections to conductive layers in staircase structures, where contact holes for lower levels are often over-etched, leading to material loss at upper levels, and the need for multiple lithography masks increases process complexity and cost.
Innovation Solution
A method involving a single lithography mask is used to form contact areas for word lines in 3D memory arrays by adding an etch-stop film over the staircase structure, allowing simultaneous formation of vertical interconnect access (VIA) contacts, which protects underlying layers during etching and reduces fabrication complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithography masks are used to form contact holes for different levels, then contact precision can be maintained, but process complexity and fabrication cost increase
Solution Approach 1:
An etch-stop layer is introduced as an intermediary element between the contact hole opening and the underlying conductive layers. This etch-stop layer enables precise control of etching depth and protects upper-level materials during etching, allowing single-mask fabrication while maintaining contact hole precision that previously required multiple masks
Solution Approach 2:
The etch-stop layer is formed in advance before contact hole etching. This preliminary action establishes a controlled termination point for the etching process, preventing over-etching and material loss at upper levels while enabling accurate contact hole formation at lower levels using a single lithography mask
2Ease of operation
If contact holes are etched through the entire stack to reach lower levels, then vertical interconnect access is achieved, but material loss occurs at upper levels due to over-etching
Solution Approach 1:
The etch-stop layer serves as a protective cushion formed beforehand at the target depth for lower-level contacts. During etching, this layer stops the etchant before it can damage or remove materials at upper levels, thereby achieving vertical interconnect access to lower levels while preventing over-etching and material loss
Solution Approach 2:
The etch-stop layer acts as an intermediary barrier that allows controlled penetration through the film stack. It enables the etching process to reach lower-level conductive layers for vertical interconnect access while simultaneously protecting upper-level materials from being etched away
3Ease of manufacture
If conventional etching processes are used without etch-stop layers, then fabrication process is simpler, but contact hole depth control and material protection are compromised
Solution Approach 1:
The etch-stop layer is introduced as a specialized intermediary layer with distinct etching characteristics. It provides a well-defined etching endpoint that enables precise control of contact hole depth, allowing the etching process to stop exactly at the desired level without requiring complex process control
Solution Approach 2:
The etch-stop layer changes the etching parameters by providing a material with different etch selectivity than the surrounding layers. This parameter change creates a natural stopping point for the etching process, improving depth control and protecting underlying structures without complicating the overall fabrication approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves fabrication yield and reduces costs by enabling the formation of semiconductor interconnects with improved precision and efficiency, balancing manufacturing throughput and process complexity.
Implementation Method 1
The method also includes etching the third oxide layer with highly selective etching and exposing the etch-stop layer of each level of the staircase structure for vertical interconnect access (VIA)
Implementation Method 2
Using chemical-mechanical-polishing (CMP) processes, for example, the top surface of the third oxide layer over each level of staircase structure is made coplanar with the top surface of the uppermost portion of the etch-stop layer
Data Source
AI summary
Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.