Selective Etch Stop Contacts for Thinner FinFET Interconnects
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to improve integration density and electrical connections in semiconductor devices while maintaining device performance, particularly in FinFETs, by reducing the overall thickness and enhancing the profiles of conductive features over gate stacks and source/drain regions.
Innovation Solution
The formation of etch stop layers on contact plugs during subsequent processing steps in semiconductor devices, such as FinFETs, allows for a reduction in device thickness and improves the profiles of conductive features, enhancing electrical connections by using epitaxial source/drain regions and stress-exerting materials to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the overall thickness of the semiconductor device is reduced to improve integration density, then integration density is improved, but maintaining device performance and electrical connections becomes more difficult
Solution Approach 1:
The patent applies local quality by forming etch stop layers at specific locations (on contact plugs) rather than uniformly throughout the device. This localized approach allows thickness reduction in non-critical areas while maintaining electrical connection integrity where needed, resolving the contradiction between improved integration density and maintained reliability of electrical connections.
2Quantity of substance
If the overall thickness of the semiconductor device is reduced to improve integration density, then integration density is improved, but device performance may deteriorate
Solution Approach 1:
The etch stop layers are strategically positioned on contact plugs to maintain device performance characteristics while enabling overall thickness reduction. This localized structural modification allows the device to achieve higher integration density without compromising the electrical performance and reliability of critical components.
3Ease of manufacture
If conventional processing is used without etch stop layers, then manufacturing is simpler, but conductive feature profiles are poor and electrical connections are degraded
Solution Approach 1:
The etch stop layers are formed in advance during subsequent processing steps, before the conductive features are deposited. This preliminary action prepares the surface with appropriate thickness and profile characteristics, enabling better adhesion and more precise conductive feature formation, thereby improving manufacturing precision without significantly complicating the overall process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach leads to better electrical connections and improved device performance by reducing the overall thickness of the semiconductor device, thereby enhancing integration density and performance characteristics.
Implementation Method 1
selectively depositing an etch stop layer on the source/drain contact
Implementation Method 2
the selectively depositing the etch stop layer is performed at least in part with an atomic layer deposition process
Implementation Method 3
using epitaxial source/drain regions to improve performance
Data Source
AI summary
Semiconductor devices and methods of manufacture are presented herein in which a etch stop layer is selectively deposited over a conductive contact. A dielectric layer is formed over the etch stop layer and an opening is formed through the dielectric layer and the etch stop layer to expose the conductive contact. Conductive material is then deposited to fill the opening.